SNLU349 October   2024

 

  1.   1
  2.   Description
  3. 1Features
  4.   4
  5.   Trademarks
  6. 2Evaluation Module Overview
    1.     Preface: Read This First
      1. 2.1.1 Sitara MCU+ Academy
      2. 2.1.2 If You Need Assistance
    2. 2.1 Introduction
    3. 2.2 Kit Contents
    4. 2.3 Specifications
    5. 2.4 Device Information
  7. 3Hardware
    1. 3.1 Power Tree
    2. 3.2 Test Points
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  9. 5Revision History

3.2 Test Points

The DP83TC812-IND-SPE is equipped with multiple test points for hardware debug and bench testing. Table 3-1 shows the test points on the board and the associated signal net.

Table 3-1 DP83TC812-IND-SPE Test Points
Test Point Signal Description
TP1 3V3_S 3.3V board supply
TP2 1V8_S 1.8V board supply
TP3 GND Ground
TP4 GND Ground
TP5 GND Ground
TP6 3V3_FB_ETH0 3.3V supply to ETH0 PHY with ferrite bead and decoupling capacitors
TP7 1V0_XTIDA_FB_ETH0 1.0V supply to ETH0 PHY with ferrite bead and decoupling capacitors
TP8 3V3_FB_ETH1 3.3V supply to ETH1 PHY with ferrite bead and decoupling capacitors
TP9 1V0_XTIDA_FB_ETH1 1.0V supply to ETH1 PHY with ferrite bead and decoupling capacitors
TP10 1V0_XTIDA 1.0V output from step-down module
TP11 ETH1_RGMII_RX_CTL RX_CTRL signal from ETH1
TP12 ETH1_RGMII_TX_CTL TX_CTRL signal from ETH1
TP13 ETH0_RGMII_RX_CTL RX_CTRL signal from ETH0
TP14 ETH0_RGMII_TX_CTL TX_CTRL signal from ETH0