Design Goals

Design Description

This high-side, current sensing solution uses a high-voltage, rail-to-rail input comparator and a p-channel MOSFET to create an over-current (OC) latch circuit. The OC output signal from the comparator is a logic-high level when the load current exceeds 10 A. The logic-high output level turns the MOSFET switch off and disconnects the load from the system supply (V_S). The comparator output also drives the bottom of the R2/R3 resistor divider which controls the OC threshold level. Under normal operating current levels, the bottom of the resistor divider is held low at ground potential. However, when the OC level is exceeded, the comparator output goes high and elevates the non-inverting input of the comparator to a level equal to V_S. Due to the integrated hysteresis of the comparator, the comparator output will remain high and thus a latched output condition is achieved. Only power-cycling V_S will remove the latched output condition. The shutdown pin could also be utilized to clear the latch if a pull-down resistor is added at the output of the comparator.

Design Notes

1. Select a comparator with rail-to-rail input common mode range to enable high-side current sensing.
2. Select a comparator with a push-pull output stage to efficiently drive the p-channel MOSFET.
3. Select a comparator with low input offset voltage to optimize accuracy.
4. Select a comparator with integrated hysteresis to create a latched-output condition.

Design Steps

1. Select the value of shunt resistor (R1) so the shunt voltage (V_SHUNT) is at least 10x greater than the comparator input offset voltage (V_IO). Note that making R1 very large will improve OC detection accuracy but will reduce supply headroom.
   ${\mathrm{V}}_{\mathrm{SHUNT}}=\left({\mathrm{I}}_{\mathrm{OC}}\times {\mathrm{R}}_1\right)\ge 10\times {\mathrm{V}}_{\mathrm{IO}}$
   $\mathrm{for} {\mathrm{I}}_{\mathrm{OC}}=10\mathrm{A} \& {\mathrm{V}}_{\mathrm{IO}}=6.5\mathrm{mV} (\max \mathrm{value} \mathrm{for} \mathrm{TLV}1805), \mathrm{VSHUNT}\ge 65\mathrm{mV}$
   $\mathrm{set} {\mathrm{R}}_1=20\mathrm{m\Omega } \mathrm{so} \mathrm{that} {\mathrm{V}}_{\mathrm{SHUNT}}=200\mathrm{mV} \mathrm{for} {\mathrm{I}}_{\mathrm{OC}}=10\mathrm{A}$
2. Since a comparator with integrated hysteresis is being utilized, the hysteresis needs to be accommodated for in the design. Note how a comparator with integrated hysteresis does not transition from high-to-low and from low-to-high at the same input voltage level. In the case of the TLV1805, the hysteresis is 14 mV and thus the transition thresholds are at ±7 mV respectively.
   TLV1805 Transition Thresholds
3. A good way to model a comparator internal hysteresis is shown below. One can think of hysteresis as offset that is intentionally added to the design. When the output of the comparator is low, a voltage source equivalent to V_HYS/2 is added in series with the inverting input pin. However, when the comparator output is high, the hysteresis is modeled as a voltage source of the same value added in series with the non-inverting input.
   Comparator Output Low
   Comparator Output High
4. Select the values of resistor divider R2 and R3 so the comparator output will transition from low-to-high when V_SHUNT exceeds 200 mV. Since the output of the comparator will be low prior to an OC condition occuring, use the Comparator Output Low model. The integrated hysteresis effectively shifts the switching threshold from V_S - 200 mV to V_S - 193 mV in the case of the TLV1805 which has an integrated hysteresis value of 14mV. Recall that 1/2 of the hysteresis is applied since hysteresis is defined as the difference between the two switching thresholds of a comparator.
5. The following equation is used to solve for R2 and R3.
   ${\mathrm{R}}_2=\frac{\left({\mathrm{V}}_{\mathrm{SHUNT}}-{\mathrm{V}}_{\mathrm{HYS}}/2\right)\times \mathrm{R}3}{{\mathrm{V}}_{\mathrm{S}}-\left({\mathrm{V}}_{\mathrm{SHUNT}}-{\mathrm{V}}_{\mathrm{HYS}}/2\right)}$
   $\mathrm{for} {\mathrm{V}}_{\mathrm{S}}=24\mathrm{V}, {\mathrm{V}}_{\mathrm{SHUNT}}=200\mathrm{mV}, {\mathrm{V}}_{\mathrm{HYS}}=14\mathrm{mV} \mathrm{and} \mathrm{R}3=1\mathrm{M\Omega }$
   $\mathrm{R}2=\frac{(200\mathrm{m}-14\mathrm{m}/2)\times 1\mathrm{M}}{24-(200\mathrm{m}-14\mathrm{m}/2)}$
   $\mathrm{R}2=8.107k\mathrm{\Omega } (\mathrm{closest} 1\% \mathrm{value} \mathrm{is} 8.06\mathrm{k\Omega })$
6. Since the goal of this design is to create a circuit that will disconnect the load from the system supply when an OC condition occurs, the output of the comparator is connected to the gate of a p-channel MOSFET switch. Recall that a p-ch MOSFET will look like a closed switch when the source to gate voltage is greater than the voltage threshold (V_SG > V_TH). Likewise, the MOSFET will look like an open-circuit when V_SG < V_TH (see figures below).
   Normal Operation = Output LOW and CLOSED Switch
   OC Condition = Output HIGH and OPEN Switch
7. Add a series resistor (R4) between the comparator output and the gate of the MOSFET to limit the output current during the transition from low to high. Keeping the current in the mA range is sufficient. Selecting a value of 10 kΩ for R1, the current is limited to 2.4 mA (24 V/10 kΩ).
8. The other goal of this design is to latch the circuit when an OC condition occurs. This is accomplished by providing feedback to the resistor divider network of R2/R3. When the output of the comparator goes high, it turns off the MOSFET and raises the non-inverting node of the comparator to a voltage level of V_S.
9. Note that V_SHUNT also reduces to 0 V since the load current is now 0 A. The hysteresis of the comparator that was previously mentioned in Design Step 2 will keep the non-inverting input 7 mV higher than the inverting input. This is what latches the comparator output in a logic high state.
10. Lastly, capacitor C1 is connected from the non-inverting input to ground to make sure that the comparator starts in the logic low output state as V_S rises upon initial power-up.

Design Simulations

DC Simulation Results

Transient Simulation Results

Design References

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

See Circuit SPICE Simulation File, SLOM456.

Design Featured Comparator

Design Alternate Comparator