Introduction

For voltage and current fault signals, it is often advantageous to latch the detection signal into the fault state until the system controller takes action to fix the faults. Latching maintains that the fault condition is acknowledged and addressed by the system controller before the latch is deliberately released. The latching functionality of comparators is typically implemented with a comparator and other discrete components. Designing and controlling a discrete latching comparator takes up board space, as well as introduces complexity to the design. This application brief explains the advantages of using TI's self-latching comparator family over discrete latching comparators.

Discrete Latching Comparator

Figure 1 Block Diagram Implementation of a Latching Comparator

Figure 2 Example Discrete Implementation of a Latching Comparator

The latch block is implemented by a Schottky diode and a resistor. During output low, the diode is forward biased and conducts to pull the non-inverting input of the comparator low. This action latches the comparator, as the non-inverting input is now a low voltage such that the inverting input can no longer cross the non-inverting input to cause an output high state. The clear function is implemented with an enhancement-mode PMOS that clears the latch on active low. The PMOS pulls the non-inverting input of the comparator up to the supply voltage to assert an output high to clear the latch.

Discrete implementations of a latching comparator add complexity to the system. Designer must account for the electrical characteristics of the latch block and the clear block. When using discrete components, such as the series resistor and Schottky diode in Figure 2, there are additional considerations to take into account to establish functionality. For example, the designer must select an appropriate resistor and Schottky diode to effectively pull the non-inverting input to a lower voltage than the input voltage at the inverting terminal. Additionally, the designer must choose and drive the pull-up PMOS to overcome the series resistor and Schottky diode to release the latch. The addition of the discrete components also affects the power dissipation of the circuit and the amount of board space the design occupies.

Integrated Self-Latching Comparator

Figure 3 Self-latching Comparator Implementation Using TLV9020L

Figure 4 Timing Diagram for TLV9020L

TLV9020L integration of the latch and clear functions simplify the design and control of the latching comparator. The lack of additional discrete components reduces the overall board space this circuit occupies. There are fewer considerations for the latch and clear, as the latch is handled internally to the TLV9020L, and the clear is a digital signal with an input low level of 0.6V and an input high level 1.2V. TLV9020L has an edge-triggered clear that offers advantages over level-triggered clears. Fault conditions can cause the clear signal to short to ground or the supply voltage, inadvertently causing the comparators to constantly be in a clear state and fail to detect fault conditions. This failure is mitigated by the TLV9020L negative edge-triggered clear signal. Overall, the TL902xL family offers improvement in functionality and design simplicity when compared to discrete latching comparators.

The TLV902xL and TLV903xL family have several power-on options differentiated by L1 and L2 options, depending on whether the user wants the self-latching comparator to power on in a latched or unlatched state.