Some power products use adaptive dead-time compensation to reduce the dead-time losses caused by the high reverse conduction voltage of GaN. The following methods are commonly used:

1. Voltage detection method: Measure the bridge-leg voltage or the VDS of an individual device to indirectly detect the charging and discharging state of the FET Coss. Once a specific threshold is reached, soft switching is considered complete. This method is the most direct and provides the highest accuracy, but it requires additional operational amplifier or comparator circuitry and has relatively poor noise immunity.
2. Current detection method: Measure the resonant tank current and calculate the theoretical dead time using an equation or lookup table. This method determines soft switching indirectly and therefore has limited accuracy. In practical applications, a certain margin must be reserved.

TI's new-generation GaN products provide Zero-Voltage Detection (ZVD) functionality. This function provides a ZVD digital signal that indicates whether the GaN device has achieved ZVS during the switching cycle. An adaptive dead-time control algorithm can be designed based on the ZVD function to reduce dead-time losses to a reasonable level, helping simplify the design of adaptive dead-time compensation in the system.

Taking the LMG3526 as an example, its ZVD operating principle is shown in Figure 2-1. When the input signal (IN) goes high, the internal logic checks whether the device has achieved ZVS during the switching cycle. Once a ZVS event meeting the specified conditions is detected, a ZVD signal pulse with a width of TWD_ZVD is output from the ZVD pin after a delay of TDL_ZVD.

It should be noted that not every ZVS event triggers ZVD. The ZVD signal is triggered only when a certain third-quadrant conduction time (T3rd_ZVD) is met. If the IDS current has just crossed zero at the time of ZVS, and the device has not entered third-quadrant conduction or the third-quadrant conduction time is insufficient, the ZVD signal will not be triggered.

Figure 2-2 shows the ZVD timing diagram of the LMG3526. It provides a more detailed explanation of the triggering conditions for the ZVD signal.

In the figure, T3rd_ZVD is the minimum third-quadrant conduction time. If the third-quadrant conduction time is less than this value, the device cannot detect ZVD. TDL_ZVD is the delay between the rising edge of the LMG3526 input pin (IN) and the rising edge of the ZVD signal output. TWD_ZVD is the hold time of the ZVD signal. When the input pin signal goes high, the logic circuit checks whether the device VDS has reached below 0V to determine whether the device has achieved zero-voltage switching during the switching cycle. Once ZVS is detected, a pulse output with a width of TWD_ZVD is generated from the ZVD pin after a delay of TDL_ZVD.

It should be noted that there is also a turn-on delay (td(ON)) between the rising edge of IN and the rising edge of the internal GaN FET gate voltage. Due to td(ON), the time at which VDS exits third-quadrant conduction in Figure 2-2 occurs later than the rising edge of IN.