SNOS975H May   2001  – June 2026 LM8262

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
    7. 5.7 Old Versus New Die Comparison
  7. 6Application and Implementation
    1. 6.1 Driving Capacitive Loads
    2. 6.2 Output Short Circuit Current and Dissipation Issues
    3. 6.3 Other Application Hints
    4. 6.4 Power Supply Recommendations
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
  8. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Third-Party Products Disclaimer
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

6.5.1 Layout Guidelines

Generally, a good high frequency layout keeps power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground causes frequency response peaking and possible circuit oscillations. General high-speed, signal-path layout suggestions include:

  • Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs. However, open up both ground and power planes around the capacitive sensitive input and output device pins. After the signal is sent into a resistor, parasitic capacitance becomes more of a band-limiting issue and less of a stability issue.
  • Use good, high-frequency decoupling capacitors (0.1μF) on the ground plane at the device power pins. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors.
  • When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces.
  • The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into the summing junction with minimal trace length to the device pin side of the resistor. The other side of these elements can have more trace length if needed to the source or to ground.