SNOSAW8F May   2008  – July 2026 LM7321 , LM7321-Q1 , LM7322 , LM7322-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Short Circuit Current and Dissipation Issues
    4. 6.4 Device Functional Modes
      1. 6.4.1 Driving Capacitive Loads
      2. 6.4.2 Electrical Overstress
      3. 6.4.3 Old Versus New Die Comparison
  8. 7 Application and Implementation
    1. 7.1 Typical Application
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.4 Thermal Information

THERMAL METRIC(2) LM732x UNIT
D (SOIC) DBV (SOT) DGK (VSSOP)
8 PINS 5 PINS 8 PINS
RθJA(1)      Junction-to-ambient thermal resistance 133.5 185.4 169.6 °C/W
(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)) – TA)/ RθJA. All numbers apply for packages soldered directly onto a PCB.
(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.