SNOU177 December   2020 LM74700-Q1


  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 I/O Connector Description
    2. 2.2 Board Setup
    3. 2.3 Schematic
  4. 3Operation
    1. 3.1 Reverse Polarity Protection
    2. 3.2 ORing Application
  5. 4EVM Board Assembly Drawings and Layout Guidelines
    1. 4.1 PCB Drawings
    2. 4.2 Bill of Materials

Reverse Polarity Protection

A dynamic voltage pulse from 12 V to –12 V is applied at the input of the LM74700DDFEVM. Figure 3-1 shows the input voltage (CH1) drops down to –12 V and the output voltage (CH2) does not go negative. Therefore, the load is protected from dynamic reverse pulses at the input. The LM74700-Q1 reacts to the negative voltage within 2 μs and it shuts down the MOSFET by pulling the gate (CH3) voltage down. The output slowly decays due to the large output capacitors and increased time constant.

GUID-87D3B46F-AF49-4B25-A2DA-66B6C1841816-low.pngFigure 3-1 Reverse Polarity 12 V to –12 V

A –12-V source is connected to the VIN input of the LM74700DDFEVM. Figure 3-2 shows that the output voltage remains at a constant 0 V in this situation. This test simulates the event of connecting a 12-V battery in the reverse direction; therefore, protecting the load from negative input voltages.

GUID-FB0C9D20-D5A8-4AD0-801B-B0E1DB43D0ED-low.pngFigure 3-2 Startup Reverse Polarity (–12 V)