SNOU196 may   2023 LM74703-Q1 , LM74704-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 I/O Connectors, Jumper and Test Points Description
      2. 2.1.2 Board Setup
    2. 2.2 Operation
      1. 2.2.1 Startup
      2. 2.2.2 FET Status Detection Test
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Drawings
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1.     Trademarks

2.1.1 I/O Connectors, Jumper and Test Points Description

I/O ConnectorDescription
J1VIN: Power input connector to the positive rail of the input power supply
J3GND: Ground connection for the power supply
J2VOUT: Power output connector to the positive side of the load
J4GND: Ground connection for the load
Test PointDescription
TP1VIN: Test point for positive of input power supply
TP2VOUT: Test point for positive side of the load
TP3FET_GOOD: Test point for FET_GOOD pin
TP4EN: Test point for EN pin
TP5, TP6GND: Test point for GND
JumperDescription
J5

Populate for on board pull-up while testing LM74704-Q1 which has open-drain FET_GOOD (Default Setting)

Do not populate while testing LM74703-Q1 as the device has push-pull FET_GOOD output

GUID-20220727-SS0I-RHCS-9SJN-4ZWZRFNN7MW4-low.svg Figure 2-1 LM74704Q1EVM Typical Application Circuit