SNVA990 August   2020  – MONTH  LM25183 , LM25183-Q1 , LM25184 , LM25184-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the LM25183, LM25184, LM25183-Q1, and LM25184-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the LM25183, LM25184, LM25183-Q1, and LM25184-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM25183, LM25184, LM25183-Q1, and LM25184-Q1 data sheets.

GUID-DD452831-8271-41E5-9720-C35BA91262AE-low.gifFigure 4-1 Pin Diagram
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
SW1VOUT = 0 V; Damage to transformerA
FB2VOUT = 0 V; Damage VIN to FBA
VIN3VOUT = 0 VB
EN/UVLO4VOUT = 0 V; Shutdown operationB
SS/BIAS5VOUT = 0 V if short during start-up. VOUT normal if short during steady-stateB
TC6Temperature compensation disabled; VOUT target will be slightly different due to Rtc||RsetC
RSET7VOUT = ISW-PEAK*tOFF*Rload*NPS/240 μs; 120 μs switchingB
GND8Normal operation.D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
SW1VOUT = 0 V; No switchingB
FB2VOUT = 0 V; 120 μs switchingB
VIN3VOUT = 0 VB
EN/UVLO4Shutdown or Regulating since EN is high impedanceB
SS/BIAS5VOUT regulating; Internal SS onlyC
TC6VOUT regulating; Temperature compensation disabledC
RSET7VOUT = 0 V; VOUT cannot be sensedB
GND8Floating GNDB
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
SW1VOUT = 0 V; Damage VIN to FB diodeA
FB2VOUT = 0 V; VOUT cannot be sensedB
VIN3VOUT regulating; Always in ACTIVE modeC
EN/UVLO4----
SS/BIAS5Current limit threshold will be lowerB
TC6VOUT = ISW-PEAK*tOFF*Rload*NPS/240 μs depending on TC; VOUT cannot be sensedB
RSET7VOUT = ISW-PEAK*tOFF*Rload*NPS/240 μs depending on TC; VOUT cannot be sensedB
GND8--
Table 4-5 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
SW1VOUT = 0 V; Damage SW to GNDA
FB2VOUT = 0 V; VOUT cannot be sensedB
VIN3Normal OperationD
EN/UVLO4VOUT regulating; Always in ACTIVE modeC
SS/BIAS5Damage to 15 V ESD on SS/BIASA
TC6Damage to 5 V ESD on TCA
RSET7Damage to 5 V ESD on RSETA
GND8VOUT = 0 VB