SNVAA87 august   2023 LMR38020

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Micro Inverter System
    2. 1.2 Typical Power Tree and Design Requirements
  5. 2Conventional Flyback Design Challenges
    1. 2.1 SSR Design Challenges
    2. 2.2 PSR Design Challenges
  6. 3New Fly-Buck Design
    1. 3.1 LMR38020 Overview
    2. 3.2 Comparison with Conventional Flyback
    3. 3.3 Design Considerations
    4. 3.4 LMR38020 Fly-Buck Design Example
  7. 4Bench Test and Result
    1. 4.1 Start Up
    2. 4.2 Typical Switching Waveforms Under Steady State
    3. 4.3 Efficiency
    4. 4.4 Load Regulation
    5. 4.5 Short Circuit
    6. 4.6 Thermal Performance
  8. 5Summary
  9. 6References

4.2 Typical Switching Waveforms Under Steady State

GUID-20230814-SS0I-KSHW-P1JX-TF1CTRHHVHBN-low.pngFigure 4-5 Steady State When VIN = 16 V, IOUT1 = 0.4 A, IOUT2 = IOUT3 = 0.1 A
GUID-20230814-SS0I-LNKV-6QHG-LMW67JTZ86QT-low.pngFigure 4-7 Steady State When VIN = 16 V, IOUT1 = 0.4 A, IOUT2 = IOUT3 = 0 A
GUID-20230814-SS0I-FJCW-FTJ8-8P0HM6RLJRQM-low.pngFigure 4-6 Steady State When VIN = 60 V, IOUT1 = 0.4 A, IOUT2 = IOUT3 = 0.1 A
GUID-20230814-SS0I-PGC7-KNK1-MK0F4NSP63XP-low.pngFigure 4-8 Steady State When VIN = 60 V, IOUT1 = 0.4 A, IOUT2 = IOUT3 = 0 A

In Figure 4-7, the fsw is higher than in the typical operation. This normally happens when VIN = VIN_MIN and D > 0.5, where toff is small, the primary current will hit the negative peak current limit. The LMR38020 turns off the LS and start a new cycle. In this case, the output regulation when VIN = VIN_MIN need to be checked to make sure that satisfies the system requirement. The VOUT2 = VOUT3 = 10 V under this application.