SNVS018AB March   2000  – June 2025 LP2985-N

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
        1. 7.1.1.1 Recommended Capacitors (Legacy Chip)
        2. 7.1.1.2 Recommended Capacitors (New Chip)
      2. 7.1.2 Input Capacitor Requirements
      3. 7.1.3 Output Capacitor Requirements
      4. 7.1.4 Noise Bypass Capacitor (CBYPASS)
      5. 7.1.5 Reverse Current
      6. 7.1.6 Power Dissipation (PD)
      7. 7.1.7 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/OFF Input Operation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Device Nomenclature
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 %
Legacy chip (A grade) –1.0 1.0
New chip –0.5 0.5
1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5
Legacy chip (A grade) –1.5 1.5
New chip –0.5 0.5
1 mA ≤ IL ≤ 150 mA Legacy chip (standard grade) –3.0 3.0
Legacy chip (A grade) –2.5 2.5
New chip –0.5 0.5
1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5
Legacy chip (A grade) –2.5 2.5
New chip –1 1
1 mA ≤ IL ≤ 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –4.0 4.0
Legacy chip (A grade) –3.5 3.5
New chip –1 1
ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V
New chip 0.002 0.014
VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032
New chip 0.002 0.032
VIN - VOUT Dropout voltage(1) IOUT = 0 mA Legacy chip 1 3 mV
New chip 1 2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5
New chip 3
IOUT = 1 mA Legacy chip 7 10
New chip 11.5 14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15
New chip 17
IOUT = 10 mA Legacy chip 40 60
New chip 98 115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 90
New chip 148
IOUT = 50 mA Legacy chip 120 150
New chip 120 145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 225
New chip 184
IOUT = 150 mA Legacy chip 280 350
New chip 180 198
IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 575
New chip 254
IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA
New chip 69 95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125
New chip 123
IOUT = 1 mA Legacy chip 75 110
New chip 78 110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170
New chip 140
IGND GND pin current IOUT = 10 mA Legacy chip 120 220 µA
New chip 175 210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 400
New chip 250
IGND GND pin current IOUT = 50 mA Legacy chip 350 600 µA
New chip 380 440
IGND  GND pin current IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 900 µA
IGND GND pin current IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C New chip 650 µA
IGND GND pin current IOUT = 150 mA Legacy chip 850 1200 µA
IGND GND pin current IOUT = 150 mA New chip 765 890 µA
IGND GND pin current IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2000 µA
IGND GND pin current IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C New chip 1060 µA
IGND GND pin current VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.08 µA
IGND GND pin current VON/OFF < 0.3 V, VIN = 16 V New chip 1.25 1.75 µA
IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C Legacy chip 0 1 µA
IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 85°C New chip 1.12 2.25 µA
IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.01 2 µA
IGND GND pin current VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C New chip 1.12 2.75 µA
VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V
VUVLO- Falling bias supply UVLO VIN falling,  –40°C ≤ TJ ≤ 125°C 1.9 V
VUVLO(HYST) UVLO hysteresis  –40°C ≤ TJ ≤ 125°C 0.130 V
VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V
New chip 0.72
Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15
New chip 0.15
High = Output ON Legacy chip 1.4
New chip 0.85
High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6
New chip 1.6
ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA
New chip 0.42
ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip -1 µA
New chip -0.9 µA
VON/OFF = 5 V Legacy chip 5 µA
New chip 0.011 µA
VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 µA
New chip 2.20 µA
IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA
New chip 300 350
IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400
New chip 375
ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB
New chip 78
Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 30 µVRMS
Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 30
Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C
Tsd- Reset, temperature decreasing 150
(1) Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.