A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the input ripple voltage. In general, the ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency.

1. Select the input capacitors with sufficient voltage and RMS current ratings. Use Equation 54 to calculate the RMS current in the input capacitors, where the worst-case operating point is at an input voltage of 10V, corresponding to 50% duty cycle.
   Equation 31. ${\mathrm{I}}_{\mathrm{C}\mathrm{I}\mathrm{N}\left(\mathrm{r}\mathrm{m}\mathrm{s}\right)}\mathrm{ }=\mathrm{ }{\mathrm{I}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\times \sqrt{\mathrm{D}\times (1-\mathrm{D})}\mathrm{ }=8\mathrm{}\mathrm{A}\mathrm{ }\times \mathrm{ }\sqrt{0.5\mathrm{ }\times \mathrm{ }(1-0.5)}=4\mathrm{}\mathrm{A}\mathrm{ }$
2. Use Equation 43 to find the required input capacitance, assuming an approximate 10% duty cycle for 48V-to-5V conversion:
   Equation 32. ${\mathrm{C}}_{\mathrm{I}\mathrm{N}}\mathrm{ }\ge \mathrm{ }\frac{\mathrm{D}\times \left(1-\mathrm{D}\right)\times {\mathrm{I}}_{\mathrm{O}\mathrm{U}\mathrm{T}}}{{\mathrm{F}}_{\mathrm{S}\mathrm{W}}\times {(\mathrm{\Delta }\mathrm{V}}_{\mathrm{I}\mathrm{N}}-{\mathrm{R}}_{\mathrm{E}\mathrm{S}\mathrm{R,Cin}}\times {\mathrm{I}}_{\mathrm{O}\mathrm{U}\mathrm{T}})}=\frac{0.1\times \left(1-0.1\right)\times 8\mathrm{}\mathrm{A}}{400\mathrm{}\mathrm{k}\mathrm{H}\mathrm{z}\mathrm{ }\times \left(480\mathrm{}\mathrm{m}\mathrm{V}-2\mathrm{}\mathrm{m}\mathrm{\Omega }\mathrm{ }\times \mathrm{ }8\mathrm{}\mathrm{A}\right)}=\mathrm{ }4.8\mathrm{}\mathrm{\mu }\mathrm{F}$

   where

   • ΔV_IN is the specification for the peak-to-peak input ripple voltage.
   • R_ESR,Cin is the effective ESR of the input capacitors.
3. Recognizing the voltage coefficient of ceramic capacitors, select four 4.7µF, 100V, X7R, 1210 ceramic input capacitors. Each capacitor has an effective capacitance value of approximately 1.3µF at 48VDC. Place these capacitors adjacent to the input pin pairs, [VIN1, PGND1] and [VIN2, PGND2].
4. Use Equation 44 to calculate the peak-to-peak ripple voltage amplitude.
   Equation 33. $∆{\mathrm{V}}_{\mathrm{I}\mathrm{N}}=\frac{{\mathrm{I}}_{\mathrm{O}\mathrm{U}\mathrm{T}}\times \mathrm{D}\times \left(1-\mathrm{D}\right)}{{\mathrm{C}}_{\mathrm{I}\mathrm{N}}\times {\mathrm{F}}_{\mathrm{S}\mathrm{W}}}+{{\mathrm{R}}_{\mathrm{E}\mathrm{S}\mathrm{R},\mathrm{C}\mathrm{i}\mathrm{n}}\times \mathrm{I}}_{\mathrm{O}\mathrm{U}\mathrm{T}}=\frac{8\mathrm{A}\times 0.1\times \left(1-0.1\right)}{4.2\mathrm{\mu }\mathrm{F}\times 400\mathrm{k}\mathrm{H}\mathrm{z}}+2\mathrm{m}\mathrm{\Omega }\times 8\mathrm{A}=0.44\mathrm{V}$
5. Connect 100nF, 100V, X7R, 0603 ceramic capacitors directly across [VIN1, PGND1] and [VIN2, PGND2] to supply the high-di/dt current during switching transitions. Such capacitors offer high self-resonant frequency (SRF) and low effective impedance above 100MHz. The result is low power-loop parasitic inductance, which reduces switch-node voltage overshoot and ringing. Refer to Section 8.5.1 for more detail.