SNVSCK4B April   2024  – October 2025 TPS3842-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
        1. 7.3.1.1 SENSE Hysteresis
      2. 7.3.2 Selecting the SENSE Delay Time
      3. 7.3.3 Selecting the RESET Delay Time
      4. 7.3.4 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Meeting the Sense and Reset Delay
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TPS3842-Q1 TPS3842A, TPS3842B DRL Package6-Pin SOT5X3Top ViewFigure 5-1 TPS3842A, TPS3842B DRL Package
6-Pin SOT5X3
Top View
TPS3842-Q1 TPS3842C DRL Package6-Pin SOT5X3Top ViewFigure 5-2 TPS3842C DRL Package
6-Pin SOT5X3
Top View

Table 5-1 Pin Functions
PINI/ODESCRIPTION
NAMESOT5X3
VDD1ISupply voltage pin.
SENSE2ISense input. Monitors input voltage based on internal voltage threshold. See Section 7.3.1 for more details.
RESET3OOutput reset signal for active-low variants. Connect RESET to pull up voltage using a pull up resistance. See Section 7.3.4 for more details.
RESET3OOutput reset signal for active-high variants. Connect RESET to pull up voltage using a pull up resistance.See Section 7.3.4 for more details.
CTS4ISense time delay: Capacitor programmable sense delay: CTS pin offers a user adjustable sense delay time when asserting a reset condition. See Section 7.3.2 for more details.
GND5—Ground pin.
CTR6IReset time delay: User-programmable reset time delay for RESET pin. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 7.3.3 for more details.