SNVSCV4 Data sheet

SNVSCV4 September 2024 LM3645

PRODUCTION DATA

6.6.1 MainReg Registers

Table 6-5 lists the memory-mapped registers for the MainReg registers. All register offset addresses not listed in Table 6-5 should be considered as reserved locations and the register contents should not be modified.

Table 6-5 MAINREG Registers

Address	Acronym	Register Name	Section
0x0	CTRL_REG1	Control Register 1	Go
0x1	CTRL_REG2	Control Register 2	Go
0x2	D_MODE_REG	Diode Mode Register	Go
0x3	STR_CTRL_REG	Strobe Control Register	Go
0x4	STR_TIME_REG	Strobe Timing Register	Go
0x5	D1_FLASH_REG	D1 Flash Current Register	Go
0x6	D2_FLASH_REG	D2 Flash Current Register	Go
0x7	D3_FLASH_REG	D3 Flash Current Register	Go
0x8	D4_FLASH_REG	D4 Flash Current Register	Go
0x9	D1_TORCH_REG	D1 Torch Current Register	Go
0xA	D2_TORCH_REG	D2 Torch Current Register	Go
0xB	D3_TORCH_REG	D3 Torch Current Register	Go
0xC	D4_TORCH_REG	D4 Torch Current Register	Go
0xD	NTC_MODE_REG	NTC Control Register	Go
0xE	NTC_ASSIGN_REG	NTC Assignment Register	Go
0xF	NTC_VOLT_REG	NTC Voltage Register	Go
0x10	NTC_READ_REG	NTC Read Register	Go
0x11	IVFM_SET_REG	Input Voltage Monitor Register	Go
0x12	CUR_RAMP_REG	Current Ramp Register	Go
0x13	FAULT_CTRL_REG	Fault Control Register	Go
0x14	FLAG_RPT_REG	Flag Report Register	Go
0x15	VOLT_FAULT_REG	Voltage Fault Report Register	Go
0x16	THERM_FAULT_REG	Thermal Fault Report Register	Go
0x17	LAST_CUR_REG1	Last Adjusted Current Register D1	Go
0x18	LAST_CUR_REG2	Last Adjusted Current Register D2	Go
0x19	LAST_CUR_REG3	Last Adjusted Current Register D3	Go
0x1A	LAST_CUR_REG4	Last Adjusted Current Register D4	Go
0x1B	DEV_INFO_REG	Device Info Register	Go

Complex bit access types are encoded to fit into small table cells. Table 6-6 shows the codes that are used for access types in this section.

Table 6-6 MainReg Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.6.1.1 CTRL_REG1 Register (Address = 0x0) [reset = 0x80]

CTRL_REG1 is shown in Figure 6-15 and described in Table 6-7.

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The CTRL_REG1 register handles control when operating in voltage output mode and configures the parameters associated with the DC/DC boost converter

Figure 6-15 CTRL_REG1 Register

7	6	5	4	3	2	1	0
VM_Voltage		Freq_Select	Curr_Lim		Boost_Mode	Mode_Priority	VM_EN
R/W-2b10		R/W-1b0	R/W-2b00		R/W-1b0	R/W-1b0	R/W-1b0

Table 6-7 CTRL_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VM_Voltage	R/W	2b10	Voltage Mode Value 2b00 = 4.0 V 2b01 = 4.5 V. Max. Output Current = 1.5A 2b10 = 5.0 V. Max. Output Current = 0.75A 2b11 = 5.2 V. Not recommended
5	Freq_Select	R/W	1b0	Sets the DC/DC Switching Frequency 1b0 = 2 MHz 1b1 = 4 MHz
4-3	Curr_Lim	R/W	2b00	Inductor Current Limit 2b00 = 2 A 2b01 = 3 A 2b10 = 4 A 2b11 = 5 A
2	Boost_Mode	R/W	1b0	Boost Mode 1b0 = Automatic 1b1 = Force Pass
1	Mode_Priority	R/W	1b0	Output Mode Priority Enable 1b0 = Voltage Mode Priority 1b1 = LED Drive Priority
0	VM_EN	R/W	1b0	Voltage Mode Enable 1b0 = Disabled 1b1 = Enabled

6.6.1.2 CTRL_REG2 Register (Address = 0x1) [reset = 0x0]

CTRL_REG2 is shown in Figure 6-16 and described in Table 6-8.

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CTRL_REG2 configures the input and output pins. The Dx_EN bits determine whether or not to enable the Dx current sources, while the upper four bits enable and disable the Strobe1, Strobe2 and Tor/Tx pins. When the Dx_EN bits are set to a '1' and the enabled outputs are assigned to either strobe pin or the tor/tx pin, the LEDs will remain off until the externally control pins are set to a '1'. If an Dx_EN bit is set to a '1' and that output is not assigned to an external control pin, the device will begin the turn on sequence assigned to that output. When used in conjunciton with the external control pins, the Dx_EN pins will remain set to a '1' (if enabled) until a fault or a time-out occurs. If the external control pins are not used and a fault or time-out occurs, the device will automatically clear the Dx_EN bit of the offending output.

Figure 6-16 CTRL_REG2 Register

7	6	5	4	3	2	1	0
TOR/TX_Mode	TOR/TX_EN	STR2_EN	STR1_EN	D4_EN	D3_EN	D2_EN	D1_EN
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 6-8 CTRL_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TOR/TX_Mode	R/W	1b0	Torch or Tx Mode Select 1b0 = Tx Mode 1b1 = Torch Mode
6	TOR/TX_EN	R/W	1b0	Tor/Tx Pin Enable 1b0 = Disabled 1b1 = Enabled
5	STR2_EN	R/W	1b0	Strobe2 Enable 1b0 = Disabled 1b1 = Enabled
4	STR1_EN	R/W	1b0	Strobe1 Pin Enable 1b0 = Disabled 1b1 = Enabled
3	D4_EN	R/W	1b0	D4 Output Enable 1b0 = Disabled 1b1 = Enabled
2	D3_EN	R/W	1b0	D3 Output Enable 1b0 = Disabled 1b1 = Enabled
1	D2_EN	R/W	1b0	D2 Output Pin Enable 1b0 = Disabled 1b1 = Enabled
0	D1_EN	R/W	1b0	D1 Output Pin Enable 1b0 = Disabled 1b1 = Enabled

6.6.1.3 D_MODE_REG Register (Address = 0x2) [reset = 0x0]

D_MODE_REG is shown in Figure 6-17 and described in Table 6-9.

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The D_MODE_REG sets the mode performance of each current source output. The DC/DC boost will adjust based upon the active modes and LEDs enabled. The mode requiring the highest output voltage will take priority.

Figure 6-17 D_MODE_REG Register

7	6	5	4	3	2	1	0
D4_MODE		D3_MODE		D2_MODE		D1_MODE
R/W-2b00		R/W-2b00		R/W-2b00		R/W-2b00

Table 6-9 D_MODE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	D4_MODE	R/W	2b00	2b00 = Off 2b01 = IR 2b10 = Torch 2b11 = Flash
5-4	D3_MODE	R/W	2b00	2b00 = Off 2b01 = IR 2b10 = Torch 2b11 = Flash
3-2	D2_MODE	R/W	2b00	2b00 = Off 2b01 = IR 2b10 = Torch 2b11 = Flash
1-0	D1_MODE	R/W	2b00	2b00 = Off 2b01 = IR 2b10 = Torch 2b11 = Flash

6.6.1.4 STR_CTRL_REG Register (Address = 0x3) [reset = 0x0]

STR_CTRL_REG is shown in Figure 6-18 and described in Table 6-10.

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The STR_CTRL_REG assigns which current sources become enabled when either of the two Strobe pins become active. Each Dx output should only be assigned to one strobe pin at a time.

Figure 6-18 STR_CTRL_REG Register

7	6	5	4	3	2	1	0
D4_STR2	D3_STR2	D2_STR2	D1_STR2	D4_STR1	D3_STR1	D2_STR1	D1_STR1
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 6-10 STR_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	D4_STR2	R/W	1b0	D4 Controlled by STR2 1b0 = Disabled 1b1 = Enabled
6	D3_STR2	R/W	1b0	D3Controlled by STR2 1b0 = Disabled 1b1 = Enabled
5	D2_STR2	R/W	1b0	D2 Controlled by STR2 1b0 = Disabled 1b1 = Enabled
4	D1_STR2	R/W	1b0	D1 Controlled by STR2 1b0 = Disabled 1b1 = Enabled
3	D4_STR1	R/W	1b0	D4 Controlled by STR1 1b0 = Disabled 1b1 = Enabled
2	D3_STR1	R/W	1b0	D3 Controlled by STR1 1b0 = Disabled 1b1 = Enabled
1	D2_STR1	R/W	1b0	D2 Controlled by STR1 1b0 = Disabled 1b1 = Enabled
0	D1_STR1	R/W	1b0	D1 Controlled by STR1 1b0 = Disabled 1b1 = Enabled

6.6.1.5 STR_TIME_REG Register (Address = 0x4) [reset = 0xA]

STR_TIME_REG is shown in Figure 6-19 and described in Table 6-11.

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STR_TIME_REG sets the flash time-out durations, as well as Strobe type

Figure 6-19 STR_TIME_REG Register

7	6	5	4	3	2	1	0
STR2_LE	STR1_LE	TO_DISABLE	FTO_MULT	FTO_DUR
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-4b1010

Table 6-11 STR_TIME_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	STR2_LE	R/W	1b0	STR2 Level or Edge Trigger 1b0 = Level 1b1 = Edge
6	STR1_LE	R/W	1b0	STR1 Level or Edge Trigger 1b0 = Level 1b1 = Edge
5	TO_DISABLE	R/W	1b0	Timeout Disable 1b0 = Time-Out Enabled 1b1 = Time-Out Disabled
4	FTO_MULT	R/W	1b0	4x Time-Out Multiplier 1b0 = 1x Gain 1b1 = 4x Gain
3-0	FTO_DUR	R/W	4b1010	Flash Time-Out Duration 4b0000 = 10 ms 4b0001 = 20 ms 4b0010 = 30 ms 4b0011 = 40 ms 4b0100 = 50 ms 4b0101 = 60 ms 4b0110 = 70 ms 4b0111 = 80 ms 4b1000 = 90 ms 4b1001 = 100 ms 4b1010 = 150 ms (Default) 4b1011 = 200 ms 4b1100 = 250 ms 4b1101 = 300 ms 4b1110 = 350 ms 4b1111 = 400 ms

6.6.1.6 D1_FLASH_REG Register (Address = 0x5) [reset = 0x0]

D1_FLASH_REG is shown in Figure 6-20 and described in Table 6-12.

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D1_FLASH_REG sets the desired Flash and IR current levels

Figure 6-20 D1_FLASH_REG Register

7	6	5	4	3	2	1	0
D1_FLASH
R/W-8b00000000

Table 6-12 D1_FLASH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D1_FLASH	R/W	8b00000000	ILED = [7.8(mA) x Code(decimal)] + 7.325 mA

6.6.1.7 D2_FLASH_REG Register (Address = 0x6) [reset = 0x0]

D2_FLASH_REG is shown in Figure 6-21 and described in Table 6-13.

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D2_FLASH_REG sets the desired Flash and IR current levels

Figure 6-21 D2_FLASH_REG Register

7	6	5	4	3	2	1	0
D2_FLASH
R/W-8b00000000

Table 6-13 D2_FLASH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D2_FLASH	R/W	8b00000000	ILED = [7.8(mA) x Code(decimal)] + 7.325 mA

6.6.1.8 D3_FLASH_REG Register (Address = 0x7) [reset = 0x0]

D3_FLASH_REG is shown in Figure 6-22 and described in Table 6-14.

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D3_FLASH_REG sets the desired Flash and IR current levels

Figure 6-22 D3_FLASH_REG Register

7	6	5	4	3	2	1	0
D3_FLASH
R/W-8b00000000

Table 6-14 D3_FLASH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D3_FLASH	R/W	8b00000000	ILED = [7.8(mA) x Code(decimal)] + 7.325 mA

6.6.1.9 D4_FLASH_REG Register (Address = 0x8) [reset = 0x0]

D4_FLASH_REG is shown in Figure 6-23 and described in Table 6-15.

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D4_FLASH_REG sets the desired Flash and IR current levels

Figure 6-23 D4_FLASH_REG Register

7	6	5	4	3	2	1	0
D4_FLASH
R/W-8b00000000

Table 6-15 D4_FLASH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D4_FLASH	R/W	8b00000000	ILED = [7.8(mA) x Code(decimal)] + 7.325 mA

6.6.1.10 D1_TORCH_REG Register (Address = 0x9) [reset = 0x0]

D1_TORCH_REG is shown in Figure 6-24 and described in Table 6-16.

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D1_TORCH_REG sets the desired D1 Torch current level

Figure 6-24 D1_TORCH_REG Register

7	6	5	4	3	2	1	0
D1_Torch
R/W-8b00000000

Table 6-16 D1_TORCH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D1_Torch	R/W	8b00000000	ILED = [1.41(mA) x Code(decimal)] + 0.525 mA

6.6.1.11 D2_TORCH_REG Register (Address = 0xA) [reset = 0x0]

D2_TORCH_REG is shown in Figure 6-25 and described in Table 6-17.

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D2_TORCH_REG sets the desired D2 Torch current level

Figure 6-25 D2_TORCH_REG Register

7	6	5	4	3	2	1	0
D2_Torch
R/W-8b00000000

Table 6-17 D2_TORCH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D2_Torch	R/W	8b00000000	ILED = [1.41(mA) x Code(decimal)] + 0.525 mA

6.6.1.12 D3_TORCH_REG Register (Address = 0xB) [reset = 0x0]

D3_TORCH_REG is shown in Figure 6-26 and described in Table 6-18.

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D3_TORCH_REG sets the desired D3 Torch current level

Figure 6-26 D3_TORCH_REG Register

7	6	5	4	3	2	1	0
D3_Torch
R/W-8b00000000

Table 6-18 D3_TORCH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D3_Torch	R/W	8b00000000	ILED = [1.41(mA) x Code(decimal)] + 0.525 mA

6.6.1.13 D4_TORCH_REG Register (Address = 0xC) [reset = 0x0]

D4_TORCH_REG is shown in Figure 6-27 and described in Table 6-19.

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D4_TORCH_REG sets the desired D4 Torch current level

Figure 6-27 D4_TORCH_REG Register

7	6	5	4	3	2	1	0
D4_Torch
R/W-8b00000000

Table 6-19 D4_TORCH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	D4_Torch	R/W	8b00000000	ILED = [1.41(mA) x Code(decimal)] + 0.525 mA

6.6.1.14 NTC_MODE_REG Register (Address = 0xD) [reset = 0x40]

NTC_MODE_REG is shown in Figure 6-28 and described in Table 6-20.

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NTC_MODE_REG Enables and disables the two NTC blocks and sets the drive current and current reduction mode

Figure 6-28 NTC_MODE_REG Register

7	6	5	4	3	2	1	0
NTC_Current		NTC2_MODE		NTC1_MODE		NTC2_EN	NTC1_EN
R/W-2b01		R/W-2b00		R/W-2b00		R/W-1b0	R/W-1b0

Table 6-20 NTC_MODE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	NTC_Current	R/W	2b01	2b00 = 25 µA 2b01 = 50 µA 2b10 = 75 µA 2b11 = 100 µA
5-4	NTC2_MODE	R/W	2b00	2b00 = Force Shutdown 2b01 = Force Torch 2b10 = Report Only 2b11 = Report Only
3-2	NTC1_MODE	R/W	2b00	2b00 = Force Shutdown 2b01 = Force Torch 2b10 = Report Only 2b11 = Report Only
1	NTC2_EN	R/W	1b0	1b0 = NTC2 is disabled 1b1 = NTC2 is enabled
0	NTC1_EN	R/W	1b0	1b0 = NTC1 is disabled 1b1 = NTC1 is enabled

6.6.1.15 NTC_ASSIGN_REG Register (Address = 0xE) [reset = 0x0]

NTC_ASSIGN_REG is shown in Figure 6-29 and described in Table 6-21.

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NTC_ASSIGN_REG determines how each of the Dx output pins responds to a NTC1 or NTC2 event. No output should be assigned to both NTC detection blocks.

Figure 6-29 NTC_ASSIGN_REG Register

7	6	5	4	3	2	1	0
NTC2_D4	NTC2_D3	NTC2_D2	NTC2_D1	NTC1_D4	NTC1_D3	NTC1_D2	NTC1_D1
R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0	R/W-1b0

Table 6-21 NTC_ASSIGN_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	NTC2_D4	R/W	1b0	1b0 = D4 Ignore 1b1 = D4 Assigned
6	NTC2_D3	R/W	1b0	1b0 = D3 Ignore 1b1 = D3 Assigned
5	NTC2_D2	R/W	1b0	1b0 = D2 Ignore 1b1 = D2 Assigned
4	NTC2_D1	R/W	1b0	1b0 = D1 Ignore 1b1 = D1 Assigned
3	NTC1_D4	R/W	1b0	1b0 = D4 Ignore 1b1 = D4 Assigned
2	NTC1_D3	R/W	1b0	1b0 = D3 Ignore 1b1 = D3 Assigned
1	NTC1_D2	R/W	1b0	1b0 = D2 Ignore 1b1 = D2 Assigned
0	NTC1_D1	R/W	1b0	1b0 = D1 Ignore 1b1 = D1 Assigned

6.6.1.16 NTC_VOLT_REG Register (Address = 0xF) [reset = 0x0]

NTC_VOLT_REG is shown in Figure 6-30 and described in Table 6-22.

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NTC_VOLT_REG sets the NTC trip voltage

Figure 6-30 NTC_VOLT_REG Register

7	6	5	4	3	2	1	0
NTC2_Set				NTC1_Set
R/W-4b0000				R/W-4b0000

Table 6-22 NTC_VOLT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	NTC2_Set	R/W	4b0000	NTC2 Trip Voltage. '0000' = 250 mV, '1111' = 1 V, 50 mV steps
3-0	NTC1_Set	R/W	4b0000	NTC1 Trip Voltage. '0000' = 250 mV, '1111' = 1 V, 50 mV steps

6.6.1.17 NTC_READ_REG Register (Address = 0x10) [reset = 0x0]

NTC_READ_REG is shown in Figure 6-31 and described in Table 6-23.

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An I2C read of the NTC_READ_REG fetches the voltage on the NTC1 and NTC2 pin for temperature readback

Figure 6-31 NTC_READ_REG Register

7	6	5	4	3	2	1	0
NTC2_READ				NTC1_READ
R-4b0000				R-4b0000

Table 6-23 NTC_READ_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	NTC2_READ	R	4b0000	NTC2 Trip Voltage. '0000' = 250 mV, '1111' = 1 V, 50 mV steps
3-0	NTC1_READ	R	4b0000	NTC1 Trip Voltage. '0000' = 250 mV, '1111' = 1 V, 50 mV steps

6.6.1.18 IVFM_SET_REG Register (Address = 0x11) [reset = 0x80]

IVFM_SET_REG is shown in Figure 6-32 and described in Table 6-24.

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The IVFM_SET_REG configures the input voltage monitor trip point, mode, hystersis and UVLO functionality. The Ramp Disable option for the Flash_Ramp should not be used if IVFM is enabled.

Figure 6-32 IVFM_SET_REG Register

7	6	5	4	3	2	1	0
UVLO_EN	IVFM_HYST	IVFM_THRES				IVFM_MODE
R/W-1b1	R/W-1b0	R/W-4b0000				R/W-2b00

Table 6-24 IVFM_SET_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UVLO_EN	R/W	1b1	1b0 = UVLO is disabled 1b1 = UVLO is enabled
6	IVFM_HYST	R/W	1b0	1b0 = 0 mV 1b1 = 50 mV
5-2	IVFM_THRES	R/W	4b0000	4b0000 = 2.5 V 4b0001 = 2.55 V 4b0010 = 2.6 V 4b0011 = 2.65 V 4b0100 = 2.7 V 4b0101 = 2.75 V 4b0110 = 2.8 V 4b0111 = 2.85 V 4b1000 = 2.9 V 4b1001 = 2.95 V 4b1010 = 3.0 V 4b1011 = 3.05 V 4b1100 = 3.1 V 4b1101 = 3.15 V 4b1110 = 3.2 V 4b1111 = 3.25 V
1-0	IVFM_MODE	R/W	2b00	2b00 = Disabled 2b01 = Stop and Hold 2b10 = Down Adjust 2b11 = Up/Down Adjust

6.6.1.19 CUR_RAMP_REG Register (Address = 0x12) [reset = 0x39]

CUR_RAMP_REG is shown in Figure 6-33 and described in Table 6-25.

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The CUR_RAMP_REG sets the ramp time of the LEDs currents in Torch, Flash and IR modes. The Ramp Disable option for the Flash_Ramp should not be used if IVFM is enabled.

Figure 6-33 CUR_RAMP_REG Register

7	6	5	4	3	2	1	0
RFU	IR_Ramp		Flash_Ramp		Torch_Ramp
R/W-1b0	R/W-2b01		R/W-2b11		R/W-3b001

Table 6-25 CUR_RAMP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RFU	R/W	1b0	Reserved
6-5	IR_Ramp	R/W	2b01	2b00 = Ramp Disabled 2b01 = 32 µs 2b10 = 64 µs 2b11 = 128 µs
4-3	Flash_Ramp	R/W	2b11	2b00 = Ramp Disabled 2b01 = 256 µs 2b10 = 512 µs 2b11 = 1024 µs
2-0	Torch_Ramp	R/W	3b001	3b000 = Ramp Disabled 3b001 = 1 ms 3b010 = 32 ms 3b011 = 64 ms 3b100 = 128 ms 3b101 = 256 ms 3b110 = 512 ms 3b111 = 1024 ms

6.6.1.20 FAULT_CTRL_REG Register (Address = 0x13) [reset = 0x19]

FAULT_CTRL_REG is shown in Figure 6-34 and described in Table 6-26.

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Enables and disables the NTC fault detection and Thermal scale back blocks, along with boost related operation

Figure 6-34 FAULT_CTRL_REG Register

7	6	5	4	3	2	1	0
SW_RESET	RFU	THERM_SB		THERM_SB_EN	NTC_OPEN_EN	NTC_SHORT_EN	LED_SHORT_EN
R/W-1b0	R-1b0	R/W-2b01		R/W-1b1	R/W-1b0	R/W-1b0	R/W-1b1

Table 6-26 FAULT_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SW_RESET	R/W	1b0	1b0 = No Reset 1b1 = Reset
6	RFU	R	1b0	Reserved
5-4	THERM_SB	R/W	2b01	Thermal Scale Back 2b00 = Force Shutdown 2b01 = Force Torch 2b10 = Report Only 2b11 = Report Only
3	THERM_SB_EN	R/W	1b1	Thermal Scale Back Enable 1b0 = TSB Disabled 1b1 = TSB Enabled
2	NTC_OPEN_EN	R/W	1b0	1b0 = NTC Open Detection Disabled 1b1 = NTC Open Detection Enabled
1	NTC_SHORT_EN	R/W	1b0	1b0 = NTC Short Detection Disabled 1b1 = NTC Short Detection Enabled
0	LED_SHORT_EN	R/W	1b1	1b0 = LED Short Detection Disabled 1b1 = LED Short Detection Enabled

6.6.1.21 FLAG_RPT_REG Register (Address = 0x14) [reset = 0x0]

FLAG_RPT_REG is shown in Figure 6-35 and described in Table 6-27.

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The FLAG_RPT_REG reports the flag events that can occur. These event flags do not need to be cleared to allow a restart and are for status only.

Figure 6-35 FLAG_RPT_REG Register

7	6	5	4	3	2	1	0
RFU		Tx	ICL	FTO4	FTO3	FTO2	FTO1
R-2b00		R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0

Table 6-27 FLAG_RPT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RFU	R	2b00	Reserved
5	Tx	R	1b0	Transmit Interrupt
4	ICL	R	1b0	Inductor Current Limit
3	FTO4	R	1b0	Flash Time-Out D4
2	FTO3	R	1b0	Flash Time-Out D3
1	FTO2	R	1b0	Flash Time-Out D2
0	FTO1	R	1b0	Flash Time-Out D1

6.6.1.22 VOLT_FAULT_REG Register (Address = 0x15) [reset = 0x0]

VOLT_FAULT_REG is shown in Figure 6-36 and described in Table 6-28.

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The VOLT_FAULT_REG register signals voltage faults that occur during any of the operating modes.

Figure 6-36 VOLT_FAULT_REG Register

7	6	5	4	3	2	1	0
UVLO	OVP	OUT_SHORT	IVFM_Trip	LED4_Short	LED3_Short	LED2_Short	LED1_Short
R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0

Table 6-28 VOLT_FAULT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UVLO	R	1b0	Under Voltage Lock Out
6	OVP	R	1b0	Over Voltage Protection
5	OUT_SHORT	R	1b0	Boost Output Short
4	IVFM_Trip	R	1b0	Input Voltage Monitor Tripped
3	LED4_Short	R	1b0	LED4 Short Detection
2	LED3_Short	R	1b0	LED3 Short Detection
1	LED2_Short	R	1b0	LED2 Short Detection
0	LED1_Short	R	1b0	LED1 Short Detection

6.6.1.23 THERM_FAULT_REG Register (Address = 0x16) [reset = 0x0]

THERM_FAULT_REG is shown in Figure 6-37 and described in Table 6-29.

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The THERM_FAULT_REG is used to report termperature related faults that occur during any of the operating modes

Figure 6-37 THERM_FAULT_REG Register

7	6	5	4	3	2	1	0
NTC2_SHORT	NTC1_SHORT	NTC2_OPEN	NTC1_OPEN	NTC2_TRIP	NTC1_TRIP	TSB	TSD
R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0	R-1b0

Table 6-29 THERM_FAULT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	NTC2_SHORT	R	1b0	NTC2 Shorted
6	NTC1_SHORT	R	1b0	NTC1 Shorted
5	NTC2_OPEN	R	1b0	NTC2 Open
4	NTC1_OPEN	R	1b0	NTC1 Open
3	NTC2_TRIP	R	1b0	NTC2 Trip
2	NTC1_TRIP	R	1b0	NTC1 Trip
1	TSB	R	1b0	Thermal Scale Back
0	TSD	R	1b0	Thermal Shutdown

6.6.1.24 LAST_CUR_REG1 Register (Address = 0x17) [reset = 0x0]

LAST_CUR_REG1 is shown in Figure 6-38 and described in Table 6-30.

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Stores the last current value reported as a fraction of full scale in the event of a current scale back event (IVFM, thermal scale back, etc)

Figure 6-38 LAST_CUR_REG1 Register

7	6	5	4	3	2	1	0
LAST_CUR
R-8b00000000

Table 6-30 LAST_CUR_REG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	LAST_CUR	R	8b00000000	Last Current Adjust Register

6.6.1.25 LAST_CUR_REG2 Register (Address = 0x18) [reset = 0x0]

LAST_CUR_REG2 is shown in Figure 6-39 and described in Table 6-31.

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Stores the last current value reported as a fraction of full scale in the event of a current scale back event (IVFM, thermal scale back, etc)

Figure 6-39 LAST_CUR_REG2 Register

7	6	5	4	3	2	1	0
LAST_CUR
R-8b00000000

Table 6-31 LAST_CUR_REG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	LAST_CUR	R	8b00000000	Last Current Adjust Register

6.6.1.26 LAST_CUR_REG3 Register (Address = 0x19) [reset = 0x0]

LAST_CUR_REG3 is shown in Figure 6-40 and described in Table 6-32.

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Stores the last current value reported as a fraction of full scale in the event of a current scale back event (IVFM, thermal scale back, etc)

Figure 6-40 LAST_CUR_REG3 Register

7	6	5	4	3	2	1	0
LAST_CUR
R-8b00000000

Table 6-32 LAST_CUR_REG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	LAST_CUR	R	8b00000000	Last Current Adjust Register

6.6.1.27 LAST_CUR_REG4 Register (Address = 0x1A) [reset = 0x0]

LAST_CUR_REG4 is shown in Figure 6-41 and described in Table 6-33.

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Stores the last current value reported as a fraction of full scale in the event of a current scale back event (IVFM, thermal scale back, etc)

Figure 6-41 LAST_CUR_REG4 Register

7	6	5	4	3	2	1	0
LAST_CUR
R-8b00000000

Table 6-33 LAST_CUR_REG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	LAST_CUR	R	8b00000000	Last Current Adjust Register

6.6.1.28 DEV_INFO_REG Register (Address = 0x1B) [reset = 0x41]

DEV_INFO_REG is shown in Figure 6-42 and described in Table 6-34.

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Stores Device Information

Figure 6-42 DEV_INFO_REG Register

7	6	5	4	3	2	1	0
DEV_ID				REV_ID
R-4b0100				R-4b0001

Table 6-34 DEV_INFO_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DEV_ID	R	4b0100	Device ID
3-0	REV_ID	R	4b0001	Revision Info