SNVU660 March   2019 TPS65653-Q1

 

  1.   TPS6565342-Q1 Technical Reference Manual
    1. 1 Introduction
    2. 2 OTP Memory Device Settings
    3. 3 Power-up and Power Down Sequence
    4. 4 Register Bits Loaded From OTP Memory
  2.   Mechanical, Packaging, and Orderable Information
    1. 5 Packaging Information
      1. 5.1 Tape and Reel Information

3 Power-up and Power Down Sequence

This section shows the power-up and power-down sequence for the device. The power-up and power-down delays for each rail are shown in Figure 1.

TPS6565342-Q1 snvu647-power-up-power-down-TPS6565342.gifFigure 1. TPS6565342-Q1 Power-up and Power Down Sequence