SNVU899 October   2024 TPS3424

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Input Power VDD
      2. 2.2.2 Pushbutton input
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks

2.1.2 EVM Test Points

Table 2-2 lists the test point connections and functional description for the device configuration. Test points are placed throughout the board to verify pin functionality.

Table 2-2 Test Points
PIN NUMBER / NAME TEST POINT DESCRIPTION
Pin1/PB1 TP1 Test point TP1 connects to PB1.
Pin8/KILL/PB2 TP2 Test point TP2 connects to PB2 for TPS3423 and KILL for TPS3424.
Pin4/SPT/INT2 TP3 Test point TP3 connects to INT2 for TPS3423 and SPT for TPS3424.
Pin5/LPT/INT1 TP4 Test point TP4 connects to INT1 for TPS3423 and LPT for TPS3424.
OUT1_EXT TP5 Test point TP5 is an input if RESET/RESET pull-up voltage is not VDD.
INT/OUT2_EXT TP6 Test point TP6 is an input if RESET2/RESET2/INT pull-up voltage is not VDD.
Pin7/INT/OUT2 TP7 Test point TP7 connects to RESET2/RESET for TPS3423 and INT for TPS3424.
Pin6/OUT1 TP8 Test point TP8 connects to RESET/RESET.
Pin3/VDD TP9/TP11 Test point TP9 and TP11connects to VDD.
Pin2/GND TP10/TP12/TP14 Test point TP10, TP12 and TP14 connects to GND.