SNVU923B December   2024  – December 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Characteristics, Test Point, and Connector Description
      1. 2.1.1 EVM Characteristics
      2. 2.1.2 EVM Connectors and Test Points
  9. 3EVM Configurations
    1. 3.1 Output Voltage Tracking
    2. 3.2 Device Configuration
  10. 4Implementation Results
    1. 4.1 Test Setup and Procedure
      1. 4.1.1 Test Setup
      2. 4.1.2 Test Procedure and Equipment
      3. 4.1.3 Precautions
  11. 5Application Curves
    1. 5.1 Efficiency
    2. 5.2 Steady State Waveforms
  12. 6Hardware Design Files
    1. 6.1 Schematic
    2. 6.2 PCB Layers
    3. 6.3 Bill of Materials
  13. 7Additional Information
    1. 7.1 Trademarks
  14. 8Revision History

3.2 Device Configuration

The LMG5126 can be configured using three pins SYNCOUT, CFG1 and CFG2. In the LMG5126EVM, these pins can be configured through the five DIP switches by selecting one of the 16 levels presented for each of the two configuration pins when the jumpers on connectors JP6 and JP7 are connecting CFG1 to DIP1 and CFG2 to DIP2, respectively. Each DIP switch has eight toggling switches that either connects or disconnects a fixed valued resistor from the configuration pins. At one time, there can be only one of the 16 levels, for each configuration pin, selected to configure the LMG5126 as seen below and according to the information given on the LMG5126 Wide-Input, 2.5MHz, Boost Converter data sheet.

The SYNCOUT-pin defines the overvoltage protection level and the ATRK, DTRK-pin 20uA current used for output voltage programming by resistor.

Table 3-1 SYNCOUT-Pin Settings
Level OVP level 20μA ATRK current

1

25V

ON

2

25V

OFF

3

35V

 ON

4

35V

 OFF

5

50V

 ON

6

50V

OFF

7

65V

 ON

8

65V

OFF

The CFG1-pin setting defines the clock dithering, the peak current limit (ICL_latch) operation, current sense voltage level and the gate driver strength.

Table 3-2 CFG1-Pin Settings
Level Spread Spectrum Sense Voltage ICL_latch Gate Drive Strength

1

DRSS ON

30mV

 Enabled Weak

2

DRSS ON

 60mV Enabled Weak

3

DRSS ON

 30mV Enabled Strong

4

DRSS ON

 60mV Enabled Strong

5

DRSS ON

 30mV Disabled Weak

6

DRSS ON

 60mV Disabled Weak

7

DRSS ON

 30mV Disabled Strong

8

DRSS ON

 60mV Disabled Strong

9

DRSS OFF

30mV

 Enabled Weak

10

DRSS OFF

 60mV Enabled Weak

11

DRSS OFF

 30mV Enabled Strong

12

DRSS OFF

 60mV Enabled Strong

13

DRSS OFF

 30mV Disabled Weak

14

DRSS OFF

 60mV Disabled Weak

15

DRSS OFF

 30mV Disabled Strong

16

DRSS OFF

 60mV Disabled Strong

The CFG2-pin defines if the device is configured for a single-or multichip setup, which then defines the operation mode of SYNCIN and SYNCOUT pin. PGOOD OVP can also be set.

Table 3-3 CFG2-Pin Settings
Level Single or Multichip SYNCOUT SYNCIN PGOOD OVP Enable

1

Single

OFF

OFF

ON

2

 Single

OFF

ON

ON

3

Primary

90°

ON

 ON

4

 Primary

120°

ON

 ON

5

 Primary

180°

ON

 ON

6

Secondary

OFF

ON

 ON

7

 Secondary

90°

ON

 ON

8

 Secondary

120°

ON

 ON

9

Single

OFF

OFF

OFF

10

Single

OFF

ON

 OFF

11

Primary

90°

ON

 OFF

12

 Primary

120°

ON

 OFF

13

 Primary

180°

ON

 OFF

14

Secondary

OFF

ON

 OFF

15

 Secondary

90°

ON

 OFF

16

 Secondary

120°

ON

 OFF

S1 through S5 are 8-bit DIP switches.

  • S1 is for SYNCOUT
    • S1-position 1 selects level 1,..., S1-position 8 selects Level 8
  • S2 and S3 are for CFG1
    • S2-position 1 selects level 1,..., S2-position 8 selects Level 8
    • S3-position 1 selects level 9,..., S3-position 8 selects Level 16
  • S4 and S5 are for CFG2
    • S4-position 1 selects level 1,..., S4-position 8 selects Level 8
    • S5-position 1 selects level 9,..., S5-position 8 selects Level 16

Select position 7 for S1 by default to set level 7 for SYNCOUT:

  • OVP level 65V
  • 20uA ATRK current source ON

Select position 2 for S3 by default to set level 10 for CFG1:

  • DRSS OFF
  • Sense voltage = 60mV
  • ICL_latch enabled
  • Gate driver strength: weak

Select position 1 for S4 by default to set level 1 for CFG2:

  • Single chip operation
  • SYNCOUT OFF
  • SYNCIN OFF
  • PGOOD OVP Enable ON