SPRACV2 November   2020 AWR1843 , AWR2243

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background – Simple Single-Chip Applications
  3. 2Cascade Incoherence Sources and Mitigation Strategies
    1. 2.1 PCB Routing Imbalances and Device Processes
    2. 2.2 Temperature Drifts
    3. 2.3 Scheduling of Run Time Calibrations
  4. 3Enabling Cascade Coherence and Improved Phase Performance
    1. 3.1 High-Level Summary
      1. 3.1.1 Sequence of Proposed Steps and Introductory Flow Diagrams
    2. 3.2 Saving RF INIT Calibration Results at Customer Factory
      1. 3.2.1 Note on LODIST Calibration
      2. 3.2.2 TX Phase Shifter Calibration and Saving Results at Customer Factory
    3. 3.3 Corner Reflector-Based Offsets Measurement at Customer Factory
      1. 3.3.1 Corner Reflector-Based Inter-Channel Imbalances
      2. 3.3.2 Corner Reflector-Based TX Phase Shifter Errors
    4. 3.4 Restoring Customer Calibration Results In-Field
      1. 3.4.1 Restore RF INIT Calibrations Results In-Field
      2. 3.4.2 Restore TX Phase Shift Calibration Results In-Field
    5. 3.5 Host-Based Temperature Calibrations In-Field
      1. 3.5.1 Disabling AWR Devices’ Autonomous Run Time Calibrations
      2. 3.5.2 Enabling Host-Based Temperature Calibrations of Inter-Channel Imbalances
      3. 3.5.3 Switching of DSP Imbalance Data
      4. 3.5.4 Enabling TX Phase Shifter’s Host-Based Temperature Calibrations
        1. 3.5.4.1 Estimating TX Phase Shift Values at Any Temperature
        2. 3.5.4.2 Temperature Correction LUTs for AWR1843TX Phase Shifter
        3. 3.5.4.3 Temperature Correction LUTs for AWR2243 TX Phase Shifter
        4. 3.5.4.4 Restoring TX Phase Shift Values – Format Conversion
        5. 3.5.4.5 Restoring TX Phase Shift Values – Transition Timing and Constraints
        6. 3.5.4.6 Typical Post-Calibration TX Phase Shifter Accuracies
        7. 3.5.4.7 Correcting for Temperature Drift While Sweeping Across Phase Settings
        8. 3.5.4.8 Amplitude Stability Across Phase Shifter Settings
        9. 3.5.4.9 Impact of Customer PCB’s 20-GHz Sync Path Attenuation on TX Phase Shifters
      5. 3.5.5 Ambient and Device Temperatures
  5. 4Concept Illustrations
  6. 5Miscellaneous (Interference, Gain Variation, Sampling Jitter)
    1. 5.1 Handling Interference In-Field
    2. 5.2 Information on TX Power and RX Gain Drift with Temperature
    3. 5.3 Jitter Between Chirp Start and ADC Sampling Start
  7. 6Conclusion
  8.   A Appendix
    1.     A.1 Terminology
    2.     A.2 References
    3.     A.3 Flow Diagrams for Proposed Cascade Coherence Scheme
    4.     A.4 LUTs for TX Phase Shifter Temperature Drift Mitigation
    5.     A.5 Circular Shift of TX Phase Shifter Calibration Data Save and Restore APIs

2.3 Scheduling of Run Time Calibrations

In single chip usage, the self-calibrations/run time calibrations reconfigure the analog sections in 10°C temperature bins to mitigate temperature effects. If the devices in a cascade system are allowed to calibrate independently (e.g. in automatic periodic calibration mode), it is possible that they make calibration updates at different times, depending on their individual temperatures. Because each device’s analog reconfiguration can change its phase responses, these calibration updates can cause abrupt jumps in inter-channel imbalances of the cascade system (see graphs illustrating this in later sections of this note). They also cause abrupt changes in the radar return signal’s absolute phase over time and corrupt advanced single-chip algorithms.

To avoid such jumps, TI recommends that the customer use a factory calibration procedure for the sensor (described in subsequent sections) and during the live operation in the field, the host processor take control of the calibration triggers by using a certain Temperature Index Update sequence to reconfigure the AWR devices and compensates for the expected phase jump in the processing.