SPRAD67A december   2022  – july 2023 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Board Design
    2. 1.2 Processor (Device) Selection
      1. 1.2.1 Availability of Tightly Coupled Memory (TCM)
    3. 1.3 Technical Documentation
    4. 1.4 Design Documentation
  5. 2 Block Diagram
    1. 2.1 Creating the Block Diagram
    2. 2.2 Selecting the Boot Mode
    3. 2.3 Confirming Pinmux (Multiplexing Compatibility)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Power (Supply) Rails
      1. 3.2.1 Core Supply
      2. 3.2.2 Peripheral Power Supply
      3. 3.2.3 Internal LDO for IO Groups (Processor IO Groups)
      4. 3.2.4 Dual-Voltage IOs (LVCMOS IOs / Processor IOs)
      5. 3.2.5 Dual-Voltage Dynamic Switching IOs for SDIO
      6. 3.2.6 VPP (eFuse ROM Programming Supply)
    3. 3.3 Determining Board Power Requirements
    4. 3.4 Power Supply Filters
    5. 3.5 Power Supply Decoupling and Bulk Capacitors
      1. 3.5.1 Note on PDN Target Impedance
    6. 3.6 Power Supply Sequencing
    7. 3.7 Supply Diagnostics
    8. 3.8 Power Supply Monitoring
  7. 4 Clocking
    1. 4.1 System Clock Input
    2. 4.2 Unused Clock Input
    3. 4.3 Clock Output
    4. 4.4 Single-ended Clock Source
    5. 4.5 Crystal Selection
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 AM64x
        2. 5.1.1.2 AM243x
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 JTAG Termination
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of the Boot Mode Configuration
    3. 6.3 Attach Device Reset
    4. 6.4 Watchdog Timer
  10. 7 Peripherals
    1. 7.1 Selecting Peripherals Across Domains
    2. 7.2 Memory
      1. 7.2.1 Processor DDR Subsystem and Device Register Configuration
    3. 7.3 Media and Data Storage Interfaces
    4. 7.4 Ethernet Interface
      1. 7.4.1 Common Platform Ethernet Switch 3-port Gigabit Ethernet (CPSW3G)
      2. 7.4.2 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
    5. 7.5 Universal Serial Bus (USB) Subsystem
    6. 7.6 Peripheral Component Interconnect Express (PCIe) Subsystem
    7. 7.7 General Connectivity Peripherals
    8. 7.8 Analog-to-Digital Converter (ADC)
      1. 7.8.1 Change Summary of AM64x / AM243x SR2.0 ADC Errata
    9. 7.9 Termination of Power Pins, Unused Peripherals and IOs
      1. 7.9.1 External Interrupt (EXTINTn)
  11. 8 Interfacing of IO Buffers and Simulations
    1. 8.1 AM64x
    2. 8.2 AM243x
  12. 9 Power Consumption and Thermal Analysis
    1. 9.1 Power Consumption
    2. 9.2 Maximum Current for Different Supply Rails
    3. 9.3 Power Modes
    4. 9.4 Guidance on Thermal Design
      1. 9.4.1 AM64x
      2. 9.4.2 AM243x
  13. 10Schematic Capture and Review
    1. 10.1 Selection of Components and Components Value
    2. 10.2 Schematic Capture
    3. 10.3 Reviewing the Schematics
  14. 11Floor Planning, Layout and Routing Guidelines
    1. 11.1 Escape Routing Guidelines
    2. 11.2 DDR Layout Guidelines
    3. 11.3 High-Speed Differential Signal Routing Guidance
    4. 11.4 Additional References for Simulation
  15. 12Device Handling and Assembly
  16. 13References
    1. 13.1 AM64x
    2. 13.2 AM243x
    3. 13.3 Common
  17. 14Terminology
  18. 15Revision History

7.8.1 Change Summary of AM64x / AM243x SR2.0 ADC Errata

One of the two pins assigned to the MMC0 PHY IO supply (VDDS_MMC0) in the SR1.0 processor is assigned as the ADC0_REFP pin in SR2.0. No compatibility issue is observed when installing a SR2.0 processor on a PCB that was designed for the SR1.0 pin assignment since the ADC0_REFP operates at the same voltage as VDDS_MMC0. However, the ADC can have performance issues if trying to use the device when a SR2.0 processor is installed on a PCB designed for SR1.0 processors since noise from the MMC0 PHY IO supply can couple directly into the ADC0_REFP pin.

SR1.0 processor cannot be installed on a PCB designed for SR2.0 processors since this PCB has a dedicated ADC0_REFP source which gets shorted to VDDS_MMC0 when a SR1.0 processor is installed.

One of the VSS pin is re-assigned to be ADC0_REFN. Currently ADC0_REFN is connected to VSS in the package. This change eliminates any direct coupling of package ground bounce into the ADC reference. This pin change does not have any impact on the PCB design since the SR1.0 VSS pin is already connected to the PCB VSS plane and we expect the new SR2.0 ADC0_REFN pin to also be connected to the PCB VSS power plane.