SPRAD67B December   2022  – September 2024 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor Selection
      1. 1.2.1 Availability of Tightly Coupled Memory (TCM)
    3. 1.3 Technical Documentation
      1. 1.3.1 Updated EVM or SK Schematics With Design, Review, and CAD Notes Added
      2. 1.3.2 FAQs to Support Custom Board Design
    4. 1.4 Design Documentation
  5. 2 Block Diagram
    1. 2.1 Constructing the Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Confirming PinMux (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power
      2. 3.1.2 Discrete Power
    2. 3.2 Power (Supply) Rails
      1. 3.2.1 Core Supply
      2. 3.2.2 Peripheral Power Supply
      3. 3.2.3 Dynamic Switching Dual-Voltage IO Supply LDO
      4. 3.2.4 Internal LDOs for IO Groups (Processor)
      5. 3.2.5 Dual-Voltage IOs (for Processor IO Groups)
      6. 3.2.6 VPP (eFuse ROM Programming) Supply
    3. 3.3 Determining Board Power Requirements
    4. 3.4 Power Supply Filters
    5. 3.5 Power Supply Decoupling and Bulk Capacitors
      1. 3.5.1 Note on PDN Target Impedance
    6. 3.6 Power Supply Sequencing
    7. 3.7 Supply Diagnostics
    8. 3.8 Power Supply Monitoring
  7. 4 Processor Clocking
    1. 4.1 Unused Clock Input
    2. 4.2 Processor External Clock Source
      1. 4.2.1 LVCMOS Digital Clock Source
      2. 4.2.2 Crystal Selection
    3. 4.3 Processor Clock Output
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG and Emulation
      1. 5.1.1 Configuration of JTAG and Emulation
        1. 5.1.1.1 AM64x
        2. 5.1.1.2 AM243x [ALV]
        3. 5.1.1.3 AM243x [ALX]
      2. 5.1.2 Implementation of JTAG and Emulation
      3. 5.1.3 Connection of JTAG Interface Signals
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of the Boot Mode Configuration
    3. 6.3 Resetting the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor Peripherals
    1. 7.1 Selecting Peripherals Across Domains
    2. 7.2 Memory (DDRSS)
      1. 7.2.1 Processor DDR Subsystem and Device Register Configuration
      2. 7.2.2 Calibration Resistor Connection for DDRSS
      3. 7.2.3 Attached Memory Device ZQ and Reset_N Connection
    3. 7.3 Media and Data Storage Interfaces
    4. 7.4 Ethernet Interface
      1. 7.4.1 Common Platform Ethernet Switch 3-port Gigabit Ethernet (CPSW3G)
      2. 7.4.2 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
    5. 7.5 Universal Serial Bus (USB) Subsystem
    6. 7.6 Peripheral Component Interconnect Express (PCIe) Subsystem
    7. 7.7 General Connectivity Peripherals
    8. 7.8 Analog-to-Digital Converter (ADC)
      1. 7.8.1 Change Summary of AM64x, AM243x SR2.0 ADC Errata
    9. 7.9 Connection of Processor Power Supply Pins, Unused Peripherals and IOs
      1. 7.9.1 External Interrupt (EXTINTn)
      2. 7.9.2 Reserved (RSVD) Pins
  11. 8 Interfacing of Processor IOs (LVCMOS or Open-Drain or Fail-Safe Type IO Buffers) and Simulations
    1. 8.1 AM64x
    2. 8.2 AM243x [ALV]
    3. 8.3 AM243x [ALX]
  12. 9 Processor Current Rating and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 AM64x
      2. 9.4.2 AM243x [ALV]
      3. 9.4.3 AM243x [ALX]
      4. 9.4.4 VTM (Voltage Thermal Management Module)
  13. 10Schematics:- Design, Capture, Entry and Review
    1. 10.1 Selection of Components and Values
    2. 10.2 Schematic Design and Capture
    3. 10.3 Schematics Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers, and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 DDR Layout Guidelines
    3. 11.3 High-Speed Differential Signals Routing Guidance
    4. 11.4 Board Layer Count and Stack-up
      1. 11.4.1 Simulation Recommendations
    5. 11.5 Reference for Steps to be Followed for Running Memory Simulation
  15. 12Custom Board Assembly and Testing
    1. 12.1 Guidelines and Board Bring-up Tips
  16. 13Device Handling and Assembly
    1. 13.1 Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14References
    1. 14.1 AM64x
    2. 14.2 AM243x
    3. 14.3 Common
  18. 15Terminology
  19. 16Revision History

7.8.1 Change Summary of AM64x, AM243x SR2.0 ADC Errata

One of the two pins assigned to the MMC0 PHY IO supply (VDDS_MMC0) in the SR1.0 processor is assigned as the ADC0_REFP pin in SR2.0. No compatibility issue is observed when installing a SR2.0 processor on a PCB that was designed for the SR1.0 pin assignment since the ADC0_REFP operates at the same voltage as VDDS_MMC0. However, the ADC can have performance issues if trying to use the device when a SR2.0 processor is installed on a PCB designed for SR1.0 processors since noise from the MMC0 PHY IO supply can couple directly into the ADC0_REFP pin.

SR1.0 processor cannot be installed on a PCB designed for SR2.0 processors since this PCB has a dedicated ADC0_REFP source which gets shorted to VDDS_MMC0 when a SR1.0 processor is installed.

One of the VSS pin is re-assigned to be ADC0_REFN. Currently ADC0_REFN is connected to VSS in the package. This change eliminates any direct coupling of package ground bounce into the ADC reference. This pin change does not have any impact on the PCB design since the SR1.0 VSS pin is already connected to the PCB VSS plane and the new SR2.0 ADC0_REFN pin is expected to also be connected to the PCB VSS power plane.