SPRADG4A January   2024  – April 2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 2Introduction
  6. 3System Description
    1. 3.1 Key System Specifications
  7. 4System Overview
    1. 4.1 Block Diagram
    2. 4.2 Basic Operation
    3. 4.3 System Design Theory
      1. 4.3.1 Peak Current Mode Control (PCMC) Implementation
      2. 4.3.2 Zero Voltage Switching (ZVS) or Low Voltage Switching (LVS)
      3. 4.3.3 Synchronous Rectification
      4. 4.3.4 Slope Compensation
  8. 5Hardware
    1. 5.1 Hardware Overview
    2. 5.2 Hardware and Test Instruments Required
    3. 5.3 TMDSCNCD263 controlCARD™ Changes
  9. 6Software
    1. 6.1 Getting Started With Firmware
      1. 6.1.1 Opening the Code Composer Studio Project
      2. 6.1.2 Software Architecture
      3. 6.1.3 Project Folder Structure
    2. 6.2 SysConfig Setup
      1. 6.2.1 EPWM Configuration
      2. 6.2.2 ADC Configuration
      3. 6.2.3 CMPSS Configuration
    3. 6.3 Incremental Builds
      1. 6.3.1 Procedure for Running the Incremental Builds - PCMC
        1. 6.3.1.1 Lab 1: Phase Overlapping Check With Open Current and Voltage Loop
          1. 6.3.1.1.1 Objective of Lab 1
          2. 6.3.1.1.2 Overview of Lab 1
          3. 6.3.1.1.3 Procedure of Lab 1
            1. 6.3.1.1.3.1 Start CCS and Open a Project for Lab 1
            2. 6.3.1.1.3.2 Build and Load the Project for Lab 1
            3. 6.3.1.1.3.3 Debug Environment Windows for Lab 1
            4. 6.3.1.1.3.4 Run the Code for Lab 1
        2. 6.3.1.2 Lab 2: Closed Current and Open Voltage Loop
          1. 6.3.1.2.1 Objective of Lab 2
          2. 6.3.1.2.2 Overview of Lab 2
          3. 6.3.1.2.3 Procedure of Lab 2
            1. 6.3.1.2.3.1 Build and Load Project for Lab 2
            2. 6.3.1.2.3.2 Debug Environment Windows for Lab 2
            3. 6.3.1.2.3.3 Run the Code for Lab 2
        3. 6.3.1.3 Lab 3: Closed Current and Closed Voltage Loop
          1. 6.3.1.3.1 Objective of Lab 3
          2. 6.3.1.3.2 Overview of Lab 3
          3. 6.3.1.3.3 Procedure of Lab 3
            1. 6.3.1.3.3.1 Build and Load Project for Lab 3
            2. 6.3.1.3.3.2 Debug Environment Windows for Lab 3
            3. 6.3.1.3.3.3 Run the Code for Lab 3
  10. 7Testing and Results
    1. 7.1 Lab 0: Basic PWM Check
    2. 7.2 Lab 1: Phase Overlapping Check With Open Current and Voltage Loop
    3. 7.3 Lab 2: Closed Current and Open Voltage Loop
    4. 7.4 Lab 3: Closed Current and Closed Voltage Loop
  11. 8References
  12. 9Revision History
6.3.1.3.3.3 Run the Code for Lab 3
  1. Follow Steps 1 to 4 of the lab 2 procedure to enable real-time mode and continuous refresh for the watch views and also for changing the continuous refresh interval for the watch view if needed.
  2. Apply an appropriate load to the PSFB system at the DC output. A load that draws around 3A–6A current at 12V output is a good starting point.
  3. Check PSFB_guivLVBus_Set_Volts. PSFB_guivLVBus_Set_Volts is targeted to be 2 at the beginning.
  4. Power the input at J1, J2 with 400V DC (200V and 300V are optional). The output voltage needs to rise up to 2V.
  5. Set PSFB_start_flag to 1. The output voltage now starts ramping up to 12V. Here is the watch view that corresponds to the operation of the system with 12V at the output with an input voltage of around 400V and a load of around approximately 5A (constant current load).
  6. Gradually increase the load (constant current load) to 20A. The output power is around 250W.
  7. By default, the synchronous rectifiers are operated in mode 2. You can change the mode of operation by changing PSFB_SR_mode variable to 0, 1, or 2 from the watch view. Observe the change in the amount of input current being drawn and changed in output voltage with different SR modes. Probe the PWM waveforms driving the synchronous rectifier switches. Do not change between different SR modes when operating at very low loads or when the output voltage is very low (less than 6V). In these cases use the default SR mode 2. To enable gating pulses for Q5 and Q6, provide 12V, 0.75A supply between pin #10 and #8 of the J17 connector.