SPRADH8 September   2024 AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 AM64x and AM243x EVMs
    2. 1.2 SoC Architecture
      1. 1.2.1 AM64x
      2. 1.2.2 AM243x
    3. 1.3 Peripherals
      1. 1.3.1 CPSW3G
      2. 1.3.2 PRU-ICSSG
    4. 1.4 Ethernet Software Architecture
    5. 1.5 Prerequisite
      1. 1.5.1 HW Prerequisite
      2. 1.5.2 SW Prerequisite
        1. 1.5.2.1 Resource Allocation - AM64x
        2. 1.5.2.2 SBL update
  5. 2 Multicore 5-Ethernet Ports Realization
  6. 3 Supported Configurations on PRU-ICSSG
  7. 4 Implementation
    1. 4.1 System Example
      1. 4.1.1 Software Architecture
      2. 4.1.2 5-Ethernet Port Example
  8. 5 Debug Steps
  9. 6 Reference Logs
  10. 7 Testing for the ICSSG0 and ICSSG1 Functionality
  11. 8 ICSSG and CPSW
  12. 9 Summary
  13. 10References

5 Debug Steps

  1. The linker.cmd file must have the inclusions required for the uncached shared memory region.
    1. This region must be specified in the syscfg.
  2. Open the ICSSG1 modules first in the syscfg-GUI.
    1. Next, open the ICSSG0 modules.
  3. The ICSSG0 MII pinconfig and the CPSW RGMII1 pinconfig share four pins.
    1. The pins are used for collision detection and CRS for two MII Ethernet ports.
    2. Disable the two signals on the ICSSG0 MII pinconfig.
      AM6442 SysConfig: ICSSG0 and ICSSG1: MII mode: Allocation to R5FSS0-0Figure 5-1 SysConfig: ICSSG0 and ICSSG1: MII mode: Allocation to R5FSS0-0
  4. Declare the INTC config for the PRUSS module in the syscfg-GUI as follows:
    1. → Pin 41: MII[0] → Channel 7
      AM6442 SysConfig: INTC CONFIG: PRU Pin-41 Figure 5-2 SysConfig: INTC CONFIG: PRU Pin-41
    2. → Pin 53: MII[1] → Channel 7
      AM6442 SysConfig: INTC CONFIG: PRU Pin-53Figure 5-3 SysConfig: INTC CONFIG: PRU Pin-53
  5. Make sure to open LwIP in all modules.
  6. SEM boards support MII PHYs only (DP83826e).
    1. As a result, only 100M is supported for testing purposes.
  7. DP83826e PHYs need reset Pins to be declared in syscfg-GUI with the following configuration:
    1. → AM64x: CONFIG_GPIO_31 → Output → GPIO0 → Pin R17 → Pull Up
      AM6442 SysConfig: GPIO Pin 31: DP83826e PHYs Reset PinsFigure 5-4 SysConfig: GPIO Pin 31: DP83826e PHYs Reset Pins
    2. CONFIG_GPIO_32 → Output → GPIO0 → Pin P16 → Pull Up
      AM6442 SysConfig: GPIO Pin 32: DP83826e PHYs Reset PinsFigure 5-5 SysConfig: GPIO Pin 32: DP83826e PHYs Reset Pins
  8. Enable the IPC for the active cores only.
    1. Do not have mismatched IPC configurations open for different cores.
    2. Make sure that the IPC is configured the same way for all cores.