SPRADH8 September 2024 AM6442
A SEM extension card on HSE port was used for adding two additional Ethernet ports for ICSSG0 and two Ethernet ports for the existing ICSSG1 Ethernet port. These four ICSSG Ethernet ports are controlled by R5FSS_0-0. This is enabled by ICSSG0 and ICSSG1 implementation. For more information, see the Ethernet PRU_ICSSG Instance-0 (PRU_ICSSG0) Usage Guide.
Users can release up to four Ethernet ports using ICSSG0 and ICSSG1. This can be either:
This particular implementation uses all four Ethernet ports of ICSSG. A user can configure two Ethernet ports from ICSSG0 and one to ISSG1.
Driver that controls CPSW shall run on R5FSS_0-1 CPU core controls a single Ethernet port in MAC mode. This implementation can be changed based on requirements and can operate two on-board RGMII Ethernet ports.
Both the cores communicate over the IPC.
Figure 4-1 SysConfig: IPC settingsNote that the system project is required to run and trigger the IPC-related code inclusions.
IPC Examples must be build as System Projects. Single core build fails since IPC code generation depends on all core contexts in the application.