SPRADP5A January   2026  – September 2026 AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stackup
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stackup
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References
  10. 7Revision History

1.3 PCB Stackup

The recommended stackup for routing designs with the AM62Px System-on-Chip (SoC) is a ten or twelve layer stack up. However, this can only be accomplished on a board with routing room with large keep-out areas. Additional layers are required if:

  • The PCB layout area is restricted, which limits the area available to spread out the signals to minimize crosstalk.
  • Other circuitry must exist in the same area, but on layers isolated from the eMMC routing.
  • Additional planes layers are needed to enhance the power supply routing or to improve EMI shielding.

Board designs that are relatively dense can require more layers to properly allow the eMMC routing to be implemented such that all rules are met.

All eMMC signals must be routed adjacent to a solid GND reference plane. When multiple GND reference planes exist in the eMMC routing area, stitching vias must be implemented nearby wherever vias transfer signals to a different GND reference plane. This is required to maintain a low-inductance return current path.

TI recommends all eMMC signals be routed as strip-line. Some PCB stackups implement signal routing on two adjacent layers. This is not recommended as crosstalk occurs on any trace routed parallel to another trace on an adjacent layer, even for a very short distance. TI recommends to route eMMC signals on PCB layers closer to the SoC within the stackup, giving the signal a shorter travel time through the via. The PCB layers farther from the SoC has longer travel times through the via, which can increase coupling between vias. Both signal and via coupling can lead to smaller timing margins.

Note a shorter via travel can mean a longer via stub (if using standard drill vias), so that is to be considered as well. Simulation can be used to determine if via stub length is an issue.

Table 1-1 PCB Stackup Specifications
NumberParameter(5)MINTYPMAXUNIT
1PCB routing plus plane layers10 or 12
2Signal routing layers6
3Full GND reference layers under eMMC routing region (1)1
4Number of reference plane cuts allowed within eMMC routing region (2)0
5Number of layers between eMMC routing layer and reference plane (3)0
6PCB routing feature size0.10mm
7PCB trace width, w0.08mm
8Point-to-Point, single-ended impedance50Ω
9Impedance control (4)Z-10%ZZ+10%Ω
(1) Ground reference layers are preferred over power reference layers. Return signal vias need to be near layer transitions.
(2) No traces must cross reference plane cuts within the eMMC routing region. High-speed signal traces crossing reference plane cuts create large return current paths, which can lead to excessive crosstalk and EMI radiation. Beware of reference plane voids caused by via anti-pads, as these also cause discontinuities in the return current path.
(3) Reference planes are to be directly adjacent to the signal layer, to minimize the size of the return current loop.
(4) Z is the nominal singled-ended impedance selected for the PCB.
(5) These specifications are to be used as a starting point for designs. TI recommends each design be extracted and simulated to make sure all requirements are met.