SPRADP5A January   2026  – September 2026 AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stackup
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stackup
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References
  10. 7Revision History

3.5.5 Pass/Fail Checks

Table 3-6 below describes the setup/hold time, slew rate, DCD, and pulse width checks for conformity to the JESD84-B51 specifications. An additional ring-back check makes sure that signals satisfy the VIH/VIL voltage level requirements. Each check is detailed separately for CLK, DATA, and CMD, as applicable. For the JEDEC checks, refer to JESD84-B51 Table 212 - HS200 Device Input Timing (JESD84-B51 Section 10.8.2) and Table 215 - HS400 Device Input Timing (JESD84-B51 Section 10.10.1).

Table 3-6 Pass/Fail Checks
Parameter CLK DATA CMD
Setup/Hold Time
  • NA
  • Run simulations with IBIS models in non-power-aware mode and profile results
  • Apply 1/4 clock cycle delay to the DAT[7:0] signals relative to the CLK signal (see Figure 3-3).
  • Use appropriate Output setup time or Output hold time from the data sheet Switching Characteristics timing table. For example, the Output setup time (HS4009) when checking setup margin and use the Output hold time (HS40011) when checking hold time margin.
  • Setup time: Overall Margin E = (A – B – C) – D, Subtract the following three values from the data sheet min output setup time parameter (A) to determine if there is enough margin for the setup requirement of the attached device:
    • B: Slowest simulated DAT signal slew measured from VCC/2 to VIH on rising transitions (see Figure 3-5) or VCC/2 to VIL on falling transitions (see Figure 3-6) at the BGA of the attached eMMC device.(5)
    • C: Adjustment from IBIS / SPICE correlation: (3)
      • 80ps for FF corner
      • 35ps for SS corner
    • D: 400ps setup time required by the attached eMMC device (per the JESD84-B51 standard(1))
  • After subtracting these three values from the data sheet min output setup time value, the Overall Margin (E) needs to be positive to pass
  • Hold time: Overall Margin E = (A – B – C) – D, Subtract the following three values from the data sheet min output hold time parameter (A) to determine if there is enough margin for the hold requirement of the attached device:
    • B: Slowest simulated DAT signal slew measured from VIL to VCC/2 on rising transitions (see Figure 3-5) or VIH to VCC/2 on falling transitions (see Figure 3-6) at the BGA of the attached eMMC device.(5)
    • C: Adjustment from IBIS / SPICE correlation: (3)
      • 80ps for FF corner
      • 35ps for SS corner
    • D: 400ps hold time required by the attached eMMC device (per the JESD84-B51 standard(1))
  • After subtracting these three values from the data sheet min output hold time value, the Overall Margin (E) needs to be positive to pass.
  • Run simulations with IBIS models in non-power-aware mode and profile results
  • Apply 1/4 clock cycle + 400ps delay to the CMD signal relative to each rising CLK transition (see Figure 3-4).
  • Use appropriate Output setup time or Output hold time from the data sheet Switching Characteristics timing table. For example, the Output setup time (HS4008) when checking setup margin and use the Output hold time (HS40010) when checking hold time margin.
  • Setup time: Overall Margin E = (A – B – C) – D, Subtract the following three values from the data sheet min output setup time parameter to determine if there is enough margin for the setup requirement of the attached device:
    • B: Slowest simulated CMD signal slew measured from VCC/2 to VIH on rising transitions (see Figure 3-5) or VCC/2 to VIL on falling transitions (see Figure 3-6) at the BGA of the attached eMMC device.(5)
    • C: Adjustment from IBIS / SPICE correlation:(3)
      • 80ps for FF corner
      • 35ps for SS corner
    • D: 1400ps setup time required by the attached eMMC device (per the JESD84-B51 standard(2))
  • After subtracting these three values from the data sheet min output setup time value, the Overall Margin (E) needs to be positive to pass
  • Hold time: Overall Margin E = (A – B – C) – D, Subtract the following three values from the data sheet min output hold time parameter to determine if there is enough margin for the hold requirement of the attached device:
    • B: Slowest simulated CMD signal slew measured from VIL to VCC/2 on rising transitions (see Figure 3-5) or VIH to VCC/2 on falling transitions (see Figure 3-6) at the BGA of attached eMMC device.(5)
    • C: Adjustment from IBIS / SPICE correlation:(3)
      • 80ps for FF corner
      • 35ps for SS corner
    • D: 800ps hold time required by the attached eMMC device (per the JESD84-B51 standard(2))
  • After subtracting these three values from the data sheet min output hold time value, the Overall Margin (E) needs to be positive to pass.
VIH/VIL (Ring-back)
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Verify the simulated CLK signal remains monotonic for both rising and falling transitions in the voltage region between (VIL - RBMargin)(4) and (VIH + RBMargin)(4).
  • Also verify the simulated CLK signal rising transition rises above (VIH + RBMargin)(4) and remains above (VIH + RBMargin)(4) until the next falling transition, where the falling transition falls below (VIL - RBMargin)(4) and remains below (VIL - RBMargin)(4) until the next rising transition.
  • The CLK signal can be non-monotonic outside the voltage region between (VIL - RBMargin)(4) and (VIH + RBMargin)(4). See an example of a good CLK signal with ring-back in Figure 3-7).
  • The CLK signal must be monotonic between (VIL - RBMargin)(4) and (VIH + RBMargin)(4). See an example of a bad CLK signal with ring-back in Figure 3-8).
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Verify the simulated DAT signals do not enter the region within VIH + RBMargin(4) and VIL - RBMargin(4) within +/-400 ps of the CLK VCC/2 crossing. See an example of a good DAT signal with ring-back in Figure 3-9. See an example of a bad DAT signal with ring-back in Figure 3-10
  • If the simulated DAT signal has ring-back, the slowest simulated DAT signal slew component used in above setup time calculation needs to be measured from the last crossing above VIH for rising edge transitions or below VIL for falling edge transitions.
  • See an example of this slew measurement for a rising DAT signal with ring-back in Figure 3-11. See an example of this slew measurement for a falling DAT signal with ring-back in Figure 3-12.
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Verify the simulated CMD signal remains monotonic for both rising and falling transitions in the voltage region between (VIL - RBMargin)(4) and (VIH + RBMargin)(4).
  • Also verify the simulated CMD signal rising transition rises above (VIH + RBMargin)(4) and remains above (VIH + RBMargin)(4) until the next falling transition, where the falling transition falls below (VIL - RBMargin)(4) and remains below (VIL - RBMargin)(4) until the next rising transition.
  • The CMD signal can be non-monotonic outside the voltage region between (VIL - RBMargin)(4) and (VIH + RBMargin)(4). See an example of a good CMD signal with ring-back in Figure 3-7).
  • The CMD signal must be monotonic between (VIL - RBMargin)(4) and (VIH + RBMargin)(4). See an example of a bad CMD signal with ring-back in Figure 3-8).
Slew Rates
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Verify the simulated CLK signal Slew Rates measured from VIL to VIH on rising transitions and measured from VIH to VIL on falling transitions at the attached eMMC device is greater to or equal to the Min Slew rate requirement of 1.45V/ns (1.125V/ns per the Slew Rate in JESD84-B51 with 30% additional margin required for IBIS simulations(3))
  • Refer to Input CLK Slew Rate in JESD84-B51 Table 215 — HS400 Device input timing.
  • Examples of passing and failing slew rates are shown for rising CLK signals in Figure 3-13 and falling CLK signals in Figure 3-14.
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Verify the simulated DAT signal Slew Rates measured from VIL to VIH on rising transitions and measured from VIH to VIL on falling transitions at the attached eMMC device is greater to or equal to the Min Slew rate requirement of 1.45V/ns (1.125V/ns per the Slew Rate in JESD84-B51 with 30% additional margin required for IBIS simulations(3))
  • If the simulated DAT signal has ring-back, then make sure the simulated DAT signal Slew Rates measured from VIL to the last VIH crossing on rising transitions and measured from VIH to the last VIL crossing on falling transitions at the attached eMMC device is greater to or equal to the Min Slew rate requirement of 1.45V/ns (1.125V/ns per the Slew Rate in JESD84-B51 with 30% additional margin required for IBIS simulations(3))
  • Refer to Input DAT Slew Rate in JESD84-B51 Table 215 — HS400 Device input timing.
  • Examples of passing and failing slew rates are shown for rising DAT signals in Figure 3-15. Examples of passing and failing slew rates are shown for falling DAT signals in Figure 3-16
  • Examples of passing and failing slew rates are shown for rising DAT signals with ring-back in Figure 3-17. Examples of passing and failing slew rates are shown for falling DAT signals with ring-back in Figure 3-18.
  • NA
DCD
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Overall Margin G = A - B - C - D - E - F, Subtract the following values from the worst simulated CLK signal duty cycle distortion measurement (B) to determine if there is enough margin:
    • A: JESD84-B51 specification (tCKDCD max 300ps)
    • B: DCD measurement from IBIS simulations – refer to tCKDCD timing definition in JESD84-B51 Figure 88 — HS400 Device Data input timing. Refer also to Section 3.5.4
    • C: Adjustment from IBIS / SPICE correlation for DCD (39ps)(3)
    • D: Adjustment from beta process (SF/FS) corners (8ps)
    • E: Impact of CLK tree and PHY level shifter (42ps)
    • F: Impact of PLL jitter (61ps)
    • After subtracting these values from the measured DCD, the Overall Margin (G) needs to be positive to pass
  • Refer to tCKDCD timing in JESD84-B51 Table 215 — HS400 Device input timing and Figure 88 — HS400 Device Data input timing.
  • Refer also to Figure 3-19.
  • NA
  • NA
Pulse Width
  • Run simulations with IBIS models in non-power aware mode and profile results
  • Overall Margin G = B - A - C - D - E - F, Subtract the following values from the worst simulated CLK pulse width measurement (B) to determine if there is enough margin:
    • B: Pulse Width from IBIS simulations – refer to tCKMPW timing definition in JESD84-B51 Figure 88 — HS400 Device Data input timing. Refer also to Section 3.5.4
    • A: JESD84-B51 specification (Min tCKMPW: 2.2ns)
    • C: Adjustment from IBIS / SPICE correlation for Pulse Width (39ps)(3)
    • D: Adjustment from beta process (SF/FS) corners (8ps)
    • E: Impact of CLK tree and PHY level shifter (42ps)
    • F: Impact of PLL jitter (61ps)
    • After subtracting these values from the measured pulse width, the Overall Margin (G) needs to be positive to pass
  • Refer to tCKMPW timing in JESD84-B51 Table 215 — HS400 Device input timing and Figure 88 — HS400 Device Data input timing.
  • Refer also to Figure 3-19.
  • NA
  • NA
(1) JEDEC HS400 Specification refers to Table 215 - HS400 Device Input Timing (eMMC JESD84-B51 Section 10.10.1).
(2) JEDEC HS200 Specification refers to Table 212 - HS200 Device Input Timing (eMMC JESD84-B51 Section 10.8.2).
(3) Results from IBIS simulations require adjustment from IBIS / SPICE correlation (IBIS simulation results are optimistic when compared to SPICE simulation results).
(4) Results from IBIS simulations require adjustment from IBIS / silicon correlation (IBIS simulation results are optimistic when compared to silicon measurements).
(5) For setup/hold time calculations, the subtraction of the slowest signal slew between VCC/2 and VIL/VIH is required because the TI data sheet timing references for these parameters are from VCC/2 of the DAT or CMD signal transition to VCC/2 of the CLK signal transition while JESD84-B51 defines the setup timing references from VIL or VIH of the DAT or CMD signal transition to VCC/2 of the CLK signal transition.
Setup/Hold Time: CLK to DATA Offset 1/4 CLK Cycle Delay Figure 3-3 Setup/Hold Time: CLK to DATA Offset 1/4 CLK Cycle Delay
Setup/Hold Time: CLK to CMD Offset 1/4 CLK Cycle + 400ps Delay Figure 3-4 Setup/Hold Time: CLK to CMD Offset 1/4 CLK Cycle + 400ps Delay
Setup/Hold Time: Slowest DATn/CMD Rising Edge Slew VCC/2 to VIH (Setup) and VIL to VCC/2 (Hold) Figure 3-5 Setup/Hold Time: Slowest DATn/CMD Rising Edge Slew VCC/2 to VIH (Setup) and VIL to VCC/2 (Hold)
Setup/Hold Time: Slowest DATn/CMD Falling Edge Slew VCC/2 to VIL (Setup) and VIH to VCC/2 (Hold) Figure 3-6 Setup/Hold Time: Slowest DATn/CMD Falling Edge Slew VCC/2 to VIL (Setup) and VIH to VCC/2 (Hold)
VIH/VIL: Example of Good CLK/CMD Signal with Ring-Back (Monotonic in VIL - RBMargin to VIH + RBMargin Range) Figure 3-7 VIH/VIL: Example of Good CLK/CMD Signal with Ring-Back (Monotonic in VIL - RBMargin to VIH + RBMargin Range)
VIH/VIL: Example of Bad CLK/CMD Signal with Ring-Back (Non-monotonic in VIL - RBMargin to VIH + RBMargin Range) Figure 3-8 VIH/VIL: Example of Bad CLK/CMD Signal with Ring-Back (Non-monotonic in VIL - RBMargin to VIH + RBMargin Range)
VIH/VIL: Example of a Good DATn Signal with Ring-Back Figure 3-9 VIH/VIL: Example of a Good DATn Signal with Ring-Back
VIH/VIL: Example of Bad DATn Signal with Ring-Back Figure 3-10 VIH/VIL: Example of Bad DATn Signal with Ring-Back
VIH/VIL: Slowest DATn Rising Edge Slew with Ring-Back (Measure to Last VIH Crossing Before Next Capture CLK Edge) Figure 3-11 VIH/VIL: Slowest DATn Rising Edge Slew with Ring-Back (Measure to Last VIH Crossing Before Next Capture CLK Edge)
VIH/VIL: Slowest DATn Falling Edge Slew with Ring-Back (Measure to Last VIL Crossing Before Next Capture CLK Edge) Figure 3-12 VIH/VIL: Slowest DATn Falling Edge Slew with Ring-Back (Measure to Last VIL Crossing Before Next Capture CLK Edge)
Slew Rates: CLK Rising Edge - Slew Rate Between VIL and VIH Must Be Faster than 1.45V/ns Figure 3-13 Slew Rates: CLK Rising Edge - Slew Rate Between VIL and VIH Must Be Faster than 1.45V/ns
Slew Rates: CLK Falling Edge - Slew Rate Between VIH and VIL Must Be Faster than 1.45V/ns Figure 3-14 Slew Rates: CLK Falling Edge - Slew Rate Between VIH and VIL Must Be Faster than 1.45V/ns
Slew Rates: DATn/CMD Rising Edge - Slew Rate Between VIL and VIH Must Be Faster than 1.45V/ns Figure 3-15 Slew Rates: DATn/CMD Rising Edge - Slew Rate Between VIL and VIH Must Be Faster than 1.45V/ns
Slew Rates: DATn/CMD Falling Edge - Slew Rate Between VIH and VIL Must Be Faster than 1.45V/ns Figure 3-16 Slew Rates: DATn/CMD Falling Edge - Slew Rate Between VIH and VIL Must Be Faster than 1.45V/ns
Slew Rates: DATn Rising Edge with Ring-Back - Slew Rate Between VIL and Last VIH Crossing Must Be Faster than 1.45V/ns Figure 3-17 Slew Rates: DATn Rising Edge with Ring-Back - Slew Rate Between VIL and Last VIH Crossing Must Be Faster than 1.45V/ns
Slew Rates: DATn Falling Slew with Ring-Back - Slew Rate Between VIH and Last VIL Crossing Must Be Faster than 1.45V/ns Figure 3-18 Slew Rates: DATn Falling Slew with Ring-Back - Slew Rate Between VIH and Last VIL Crossing Must Be Faster than 1.45V/ns
Measuring Pulse Width for DCD and Pulse Width Measurements Figure 3-19 Measuring Pulse Width for DCD and Pulse Width Measurements
Note: VCC/2 scales with the IO voltage for TT, SS, FF corner being simulated.