SPRADP5A January   2026  – September 2026 AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stackup
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stackup
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References
  10. 7Revision History

3.5.3 Simulation Best Practices

Guidance provided is not specific for any EDA tool. The following list of best practices can be implemented in the simulator of choice by working with the appropriate EDA vendor:

  • While simulating with S-parameters, it is highly recommended to include options which allow smoothing of the S-parameters to help simulator convergence and result in accurate waveforms
  • Timestep and accuracy settings in the simulator need to be set appropriately to enable simulator convergence and result in accurate waveforms
  • Extract board signal and board power models up to 5GHz
  • Extracted S-parameters need to be checked for causality and passivity. Non-causal or non-passive S-parameters can result in inaccurate results
  • It is recommended to perform a short 10 bit to 15 bit simulation to validate the simulation setup and connectivity, before running the full set of simulations with attack patterns
  • It is recommended to check the impedance of the signal traces in the extracted model to verify that the variations in impedance are within acceptable limits