SPRADP5 January   2026 AM62P , AM62P , AM62P-Q1 , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stack-Up
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References

4.3 Signal Routing

The example signal routing in Figure 4-3 and Figure 4-4 below shows the eMMC signal routing used on the SK-AM62P-LP (PROC164E2) 12-layer PCB design.

The eMMC signals CMD and DAT[7:0] are routed entirely as stripline on layer 3 with target impedance of 50Ω.

CLK is routed with target impedance of 50Ω from the SoC pin to a series termination resistor on the bottom layer beneath to the SoC before transitioning to Layer 3 with target impedance of 50Ω.

DS is routed with target impedance of 50Ω from the eMMC pin to a series termination resistor on the bottom layer beneath the eMMC device before transitioning to Layer 3 with target impedance of 50Ω.

GND stitching vias facilitate a continuous GND return path for the CLK and DS signals on both sides of the vias to the series termination resistor on the bottom layer.

This layout was demonstrated through simulations to satisfy with margin the Pass/Fail checks mentioned above to show compliance with the JEDEC specifications.

SK-AM62P-LP (PROC164E2) eMMC Signal Routing - CMD and DAT[7:0] Figure 4-3 SK-AM62P-LP (PROC164E2) eMMC Signal Routing - CMD and DAT[7:0]
SK-AM62P-LP (PROC164E2) eMMC Signal Routing - CLK and DS Figure 4-4 SK-AM62P-LP (PROC164E2) eMMC Signal Routing - CLK and DS
Table 4-2 Example eMMC Trace Impedance Summary
Layer Signals Single Ended Impedance (Ω)
L3 eMMC CLK(1), CMD, DAT[7:0], DS(1) 49.87
L12 eMMC CLK(1), DS(1) 50.13
(1) CLK and DS transition to L12 (bottom layer) to series termination resistors then transition back to L3 for remainder of the route