SPRADP5 January   2026 AM62P , AM62P , AM62P-Q1 , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stack-Up
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References

2.1 eMMC Introduction

eMMC is a managed memory device specification governed by the JEDEC standard JESD84-B51, Embedded Multi-Media Card (e•MMC) Electrical Standard (5.1). This standard strives to support high throughput for large data transfers without compromising small random data accesses (code) while maintaining low power consumption required by mobile devices. Its 11-signal bus consists of Clock (CLK), Command (CMD), Data Strobe (DS), and Data (DAT[7:0]) with 3 different bus widths: 1-bit (default), 4-bit, and 8-bit. Clock frequencies range from 0-200MHz, with single- and dual-data-rate options for up-to 400MB/s max data transfer rate (HS400). In HS400 mode, the IO voltage is fixed at 1.8V.

The following sections detail the routing specification and layout guidelines for an eMMC interface with a focus on the power delivery for the AM62Px eMMC PHY.

Note: The maximum eMMC data rate supported by the AM62Px processor is defined in the AM62Px Sitara™ Processors Data Sheet. Refer to HS4005 Cycle time, MMC0_CLK in the MMC0 Switching Characteristics – HS400 Mode table.