SPRADP5A January   2026  – September 2026 AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Px eMMC HS400 IBIS Model Simulation Methodology
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stackup
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2eMMC Board Design and Layout Guidance
    1. 2.1 eMMC Introduction
    2. 2.2 eMMC Signal Termination
    3. 2.3 Signal Routing Specification
    4. 2.4 Power Supply Design
  6. 3eMMC Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 Capacitor Loop Inductance
    4. 3.4 AC Impedance
    5. 3.5 IBIS Model Simulations
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Bit Patterns
      3. 3.5.3 Simulation Best Practices
      4. 3.5.4 Simulation Strategy and Examples
      5. 3.5.5 Pass/Fail Checks
  7. 4Design Example
    1. 4.1 Stackup
    2. 4.2 Power Routing
    3. 4.3 Signal Routing
  8. 5Summary
  9. 6References
  10. 7Revision History

3.3 Capacitor Loop Inductance

High frequency decoupling capacitors must have a low loop inductance to respond to instantaneous current demands. This localized response also helps to prevent supply noise from one supply pin from coupling into another pin that shares the same supply. An inductive path to the decoupling capacitors only adds to the fixed inductance of the SoC package.

High frequency decoupling capacitors must have low embedded series inductance (ESL). The SK-AM62P-LP (PROC164E2) uses ceramic 0.1uF 10V 10% 0201 capacitors with an ESL of approximately 0.146nH. The placement of each capacitor and connectivity through trace and vias must be kept short and wide to minimize total loop inductance.

The 1.8V VDDS_MMC0 eMMC PHY IO supply is typically shared among eMMC and non-eMMC supplies. Each supply pin requires decoupling capacitors placed in close proximity to the respective supply pin. The below table shows the loop inductance of each capacitor on the 1.8V rail used by the SK-AM62P-LP (PROC164E2).

Check the loop inductance with the following steps:

  1. Extract loop inductance for all high frequency decoupling capacitors on other 1.8V power rails shorted to VDDS_MMC0.
    1. Loop inductance must be extracted with a 3-D field solver. 2.5D solvers do not suffice for inductance extractions.
    2. The inductance extraction must be from the pads of the decoupling capacitor to the SoC BGAs.
  2. Compare the extracted loop inductance to the target values published in Table 3-1.
    1. The loop inductance for all decoupling capacitors on VDDS_MMC0 and other 1.8V power nets shorted to VDDS_MMC0 needs to be smaller than the target to pass loop inductance checks.
Table 3-1 Loop Inductance of Capacitors on VDDS_MMC0 and Other Shared 1.8V Power Rails
Supply Name Description Target
VDDS_MMC0 1.8V eMMC0 PHY IO Supply ≤ 0.72nH
VDDSHVn(1), VDDSHV_CANUART, VDDSHV_MCU 1.8V IO supplies shared with VDDS_MMC0(2) ≤ 1.37nH
(1) n = 0-6
(2) Consider only 1.8V IO supplies shared with VDDS_MMC0 supply.