SPRADT3 June   2026 AWR2188

 

  1.   1
  2.   Abstract
  3. 1Introduction to AWR2188
  4. 2Hardware Architecture and Design
    1. 2.1 Radar System Architecture
    2. 2.2 AWR2188 Radar Hardware Design
    3. 2.3 SOP Pin Configuration
    4. 2.4 AWR2188 Reset and RBL Boot Process
  5. 3AWR2188 External Processor Software Configuration
    1. 3.1 External Processor Powers on and Configures MSS
    2. 3.2 DFP Image Download
    3. 3.3 MSS Application Boot and Configuration
  6. 4AWR2188 SPI/I2C Configuration and Signal Analysis
    1. 4.1 SPI Boot Configuration and Timing
    2. 4.2 I2C Boot Configuration and Timing
  7. 5References
  8. 6Modification History

2.3 SOP Pin Configuration

The first operation of AWR2188 after power-on is to read the state of the Sense-on-Power (SOP) pins. Table 2-1 are the SOP modes and corresponding pins for AWR2188.

Table 2-1 Sense-on-Power (SOP) Lines and Boot Modes
Functions Signal Description Pin Number
SOP – SOP[4:0] SOP0 (Multiplexed with TDO) SOP 0 - controls boot behavior AF8
SOP1 (Multiplexed with FRM_SYNCOUT) SOP 1 - controls boot behavior AF3
SOP2 (Multiplexed with PMIC_CLKOUT) SOP 2 - controls boot behavior AG5
SOP3 (Multiplexed with MCU_CLKOUT) SOP 3 - controls cascade/non-cascade AG6
SOP4 (Multiplexed with QSPI_0) SOP 4 - controls 40 MHz or 50 MHz crystal AG27
SOP Mode Description SOP[2:0]
Functional Mode SPI Main deployment mode. Firmware patches are loaded from an external processor via SPI or from Flash via QSPI, functional firmware execution begins and device is controlled via SPI commands 0 0 1
Device Management Mode Flash programming mode. Image files (patches) are downloaded to a serial flash (SFLASH) via a burn tool that transfers the image files over UART 1 0 1
Functional Mode I2C Load firmware patches via I2C, and then functional firmware begins execution 1 1 1
SOP Mode Description SOP[3]
Cascade Mode 0: Single-chip AWR2188 1: Multi-chip cascade mode 1 or 0
SOP Mode Description SOP[4]
Crystal Selection 0: 40MHz 1: 50MHz 1 or 0