SPRUIG8I January 2018 – December 2023
The --debug_software_pipeline option places additional software pipeline feedback in the generated assembly file.
If software pipelining succeeds for a given loop, and the --debug_software_pipeline option was used during the compilation process, a register usage table is added to the software pipelining information comment block in the generated assembly code.
The numbers on each row represent the cycle number within the loop kernel.
Each column represents one register on the C7000. The registers are labeled in the first three rows of the register usage table and should be read columnwise.
An * in a table entry indicates that the register indicated by the column header is live on the kernel execute packet indicated by the cycle number labeling each row.
An example of the register usage table follows:
;* Register Usage Tables:
;*
;* +----------------------------------+----------------------------------+
;* | ASIDE | BSIDE |
;* +----------------+--------+--------+----------------+--------+--------+
;* | "Axx" | "ALx" | "AMx" | "VBxx" | "VBLx" | "VBMx" |
;* +----------------|--------|--------|----------------|--------|--------+
;* |0000000000111111|00000000|00000000|0000000000111111|00000000|00000000|
;* |0123456789012345|01234567|01234567|0123456789012345|01234567|01234567|
;* +----------------|--------|--------|----------------|--------|--------+
;* 0: |* *** |* |*** | * |*** |******* |
;* 1: |* *** |** | ** | ** |*** |* ***** |
;* 2: |* **** |* |*** | * ** |*** |* **** |
;* 3: |****** |* | ** | ** ** |** |* **** |
;* 4: |** *** |* | ** |****** |*** | **** |
;* 5: |** *** |* | ** |*** ** |** |** **** |
;* 6: |* *** |* | ** |*** ** |* |******* |
;* 7: |* *** |* |*** |* ** |** |******* |
;* +----------------+--------+--------+----------------+--------+--------+
;*
;* +----------------+ +--------+ +-------+
;* | "Dxx" | | "Px" | |"CUCRx"|
;* +----------------+ +--------+ +-------+
;* |0000000000111111| |00000000| |0000 |
;* |0123456789012345| |01234567| |0123 |
;* +----------------+ +--------+ +-------+
;* 0: |* | | | | |
;* 1: |* | | | | |
;* 2: |* | | | | |
;* 3: |* | | | | |
;* 4: |* | | | | |
;* 5: |* | | | | |
;* 6: |* | | | | |
;* 7: |* | | | | |
;* +----------------+ +--------+ +-------+
This example shows that on cycle 0 (the first execute packet) of the loop kernel, registers A0, A3, A4, A5, A6, AL0, AM0, AM1, AM2, VB5, VBL0, VBL1, VBL2, VBM0, VBM1, VBM2, VBM3, VBM4, VBM5, VBM6, and D0 are all live during this cycle.