SPRUIJ9C April   2018  – October 2025

 

  1.   1
  2. 1Read This First
    1. 1.1 About This Manual
    2. 1.2 Related Documentation From Texas Instruments
  3.   Trademarks
  4.   6
  5. 2AM5724x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware
    1. 2.1  Introduction
      1. 2.1.1 Description
      2. 2.1.2 REACH Compliance
      3. 2.1.3 System View
    2. 2.2  Functional Description
      1. 2.2.1 Processor
      2. 2.2.2 Clocks
      3. 2.2.3 Reset Signals
    3. 2.3  Power Supplies
      1. 2.3.1 Power Source
      2. 2.3.2 TPS6590379 PMIC
      3. 2.3.3 AVS Control
      4. 2.3.4 Other Power Supplies
    4. 2.4  Configuration/Setup
      1. 2.4.1 Boot Configuration
      2. 2.4.2 I2C Address Assignments
      3. 2.4.3 SEEPROM Header
      4. 2.4.4 JTAG Emulation
    5. 2.5  Memories Supported
      1. 2.5.1 DDR3L SDRAM
      2. 2.5.2 SPI NOR Flash
      3. 2.5.3 Board Identity Memory
      4. 2.5.4 SD/MMC
      5. 2.5.5 eMMC NAND Flash
    6. 2.6  Ethernet Ports
      1. 2.6.1 100Mb Ethernet Ports on PRU-ICSS
      2. 2.6.2 Gigabit (1000Mb) Ethernet Ports
    7. 2.7  USB Ports
      1. 2.7.1 Processor USB Port 1
      2. 2.7.2 Processor USB Port 2
      3. 2.7.3 FTDI USB Port
    8. 2.8  PCIe
    9. 2.9  Video Input and Output
      1. 2.9.1 Camera
      2. 2.9.2 HDMI
      3. 2.9.3 LCD
    10. 2.10 Industrial Interfaces
      1. 2.10.1 Profibus
      2. 2.10.2 DCAN
      3. 2.10.3 RS-485
    11. 2.11 User Interfaces
      1. 2.11.1 Tri-color LEDs
      2. 2.11.2 Industrial Inputs
      3. 2.11.3 Industrial Outputs / LEDs
    12. 2.12 Pin Use Description
      1. 2.12.1 Functional Interface Mapping
      2. 2.12.2 GPIO Pin Mapping
    13. 2.13 Board Connectors
    14. 2.14 EVM Important Notice
  6. 3Known Deficiencies in AM5724x IDK EVM
    1. 3.1  Power solution not sufficient for full PCIe plug-in card compliance
    2. 3.2  AM574x IDK EVM does not support eMMC HS200 mode
    3. 3.3  PCIe PERSTn line not in proper state at start-up
    4. 3.4  EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and PRU2
    5. 3.5  HDQ implementation not correct
    6. 3.6  Removing the power plug and inserting it again while the power supply is energized may cause damage
    7. 3.7  Software shutdown of PMIC not operational
    8. 3.8  PMIC implementation does not support required SOC shut-down sequence
    9. 3.9  USB port providing UART console and XDS100 emulation not isolated from EVM board supplies
    10. 3.10 Need 47-µf capacitor at camera header
    11. 3.11 Decoupling capacitors do not reflect AM574x PDN recommendations
    12. 3.12 CCS System Reset fails
    13. 3.13 AM574x IDK EVM design contains 2 clamp circuits that may not be necessary
    14. 3.14 Crystal connected to osc0 needs to have 50 ppm or better long term accuracy
    15. 3.15 Software must program the CDCE913 for 0-pf load capacitance
    16. 3.16 PHY address LSB for U9 and U15 can be latched incorrectly
  7. 4Revision History

2.7.1 Processor USB Port 1

Processor port USB1 is implemented only as a USB host (master). It supports both USB2.1 (high speed) and USB3.0 (super speed) data rates. The connector on the board, J23, is a USB3.0 Standard A-type connector. The ESD devices implemented on this USB port are the TPD2EUSB30 for the DP and DM lines and the TPD4E05U06 for the super-speed pairs.

Since processor USB port 1 supports host mode, it has the capability to drive 5.0V power on the VBUS pin. The TPS2065D load switch is controlled by the USB1_DRVVBUS pin for this purpose.