SPRUIT0B December   2019  – October 2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   4
  5. 1Introduction
    1. 1.1 Key Features
  6. 2Infotainment Expansion Board Overview
    1. 2.1 Infotainment Expansion Board Identification
    2. 2.2 Infotainment Expansion Board Component Identification
  7. 3Infotainment Expansion Board - User Setup/Configuration
    1. 3.1 Interfacing Infotainment Expansion Board With CP Board
      1. 3.1.1 Board Assembly Procedures
    2. 3.2 Power Requirements
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM Configuration DIP Switch
  8. 4Infotainment Expansion Board Hardware Architecture
    1. 4.1  Infotainment Expansion Board Hardware Top Level Diagram
    2. 4.2  Expansion Connectors
    3. 4.3  Board ID EEPROM
    4. 4.4  Audio Codec Interface
      1. 4.4.1 Port Mapping
    5. 4.5  FPD link De-Serializer Interface (Audio)
    6. 4.6  DIR Interface
    7. 4.7  DIT Interface
    8. 4.8  Legacy Audio/JAMR3 Connectors
    9. 4.9  VIN/VOUT Mux Selection
    10. 4.10 HDMI Interface Bridge
    11. 4.11 FPD Link Display Serializer Interface
    12. 4.12 Parallel Camera Interface
      1. 4.12.1 Camera Clock
      2. 4.12.2 LI Camera Module Connector
      3. 4.12.3 OV Camera Module Connector
  9. 5Jacinto7 EVM Interface/IO Mapping
    1. 5.1 Interface Mapping
    2. 5.2 Infotainment Board GPIO Mapping
    3. 5.3 I2C Address Mapping
  10. 6Revision History

4.12 Parallel Camera Interface

There are two camera module connectors present on infotainment expansion board to support parallel camera interface:

  • 32 pin Omni Vision camera module connector
  • 36 Pin Leopard imaging camera module connector

Parallel camera data & SYNC signals from both connectors are connected to a 2x 2:1 Camera selection MUX IC Part#: SN74AVCB164245VR. GPIO signal CAM_SEL_OV# is used to select between OV-camera and LI-Camera modules. By default, OV camera signal path is enabled. For GPO mapping, see Section 5.2.

The output of camera selection mux is connected to VIN/VOUT selection mux. To route the parallel camera signals to VPFE port of SoC, see Table 4-9 and Section 5.2.

SPI, Reset, PCLK and Power down signals are terminated with Camera connector through 3x level translation circuit IC Part# SN74AVC4T245DGVR (U3, U4 and U5). Camera I2C signals are level translated using IC part# PCA9306DCT.

Note:

Camera modules will not be the part of delivery kit.