SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.7 UART Interface

The two UART ports MAIN_UART0 and MCU_UART0 provided by AM64x are connected to two channel USB to UART Bridge (CP2105) and terminated to a USB Micro B Connector J11. Two ports of the CP2105 are connected to MAIN_UART0 and MCU_UART0 with the RXD, TXD, RTS, and CTS signals.

The USB interface circuit is used in bus powered configuration and a voltage translator (SN74AVC4T245) is used to isolate AM64x IOs. The CP2105 includes an on-chip 5-V to 3.45-V voltage regulator. LD18 is used to indicate power good status of CP2105. This allows the CP2105 to be configured as a USB bus-powered device. The voltage regulator output appears on the VDD pin and can be used to drive the IO supply and one of the supply rails of the voltage translator. Internally, the same VDD is used to operate the core section of CP2105. CP2105 also includes an integrated clock and hence no external crystal is required. MAIN_UART0 and MCU_UART0 from SOC are at 3.3-V IO level. The devices use the internal POR circuit. For normal operation, the nRST pin must be pulled up to 3V3 supply through the 10K resistor. Because the device operates in bus powered configuration, VBUS from the USB connector must be connected to the “REGIN” pin of CP2105 to serve as the input for the internal regulator.

A ESD protection is provided on USB signals to steer ESD current pulses to VCC or GND. TPD4E004 protects against ESD pulses up to ±15-kV Human-Body Model (HBM) as specified in IEC 61000-4-2 and provides ±8-kV contact discharge and ±12- kV air-gap Discharge.

Figure 4-7 shows the dual UART to USB bridge connection with AM64x.

GUID-88866F66-23DA-4685-B985-D91F2092FF97-low.png Figure 4-7 UART Interface