SPRUJ64 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Key Features
  4. 2AM64x SKEVM Overview
    1. 2.1 Board Version Identification
  5. 3Functional Block Diagram
  6. 4System Description
    1. 4.1  Clocking
      1. 4.1.1 Ethernet PHY Clock
      2. 4.1.2 AM64x SoC Clock
    2. 4.2  Reset
    3. 4.3  Power Requirements
      1. 4.3.1 Power Input
      2. 4.3.2 USB Type-C Interface for Power Input
      3. 4.3.3 Power Fault Indication
      4. 4.3.4 Power Supply
      5. 4.3.5 Power Sequencing
      6. 4.3.6 SOC Power
    4. 4.4  Configuration
      1. 4.4.1 Boot Modes
    5. 4.5  JTAG
    6. 4.6  Test Automation
    7. 4.7  UART Interface
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 MMC Interface
        1. 4.8.2.1 Micro SD Interface
        2. 4.8.2.2 WiLink Interface
        3. 4.8.2.3 OSPI Interface
        4. 4.8.2.4 Board ID EEPROM Interface
    9. 4.9  Ethernet Interface
      1. 4.9.1 DP83867 PHY Default Configuration
      2. 4.9.2 DP83867 – Power, Clock, Reset, Interrupt, and LEDs
      3. 4.9.3 Industrial Application LEDs for Indication
    10. 4.10 USB 3.0 Interface
    11. 4.11 PRU Connector
    12. 4.12 User Expansion Connector
    13. 4.13 MCU Connector
    14. 4.14 Interrupt
    15. 4.15 I2C Interface
    16. 4.16 IO Expander (GPIOs)
  7. 5Known Issues and Modifications
    1. 5.1 Issue 1 - Silkscreen Missprint on Initial Board Batch
  8. 6Revision History

4.3.6 SOC Power

The SoC Core voltage (VDD_CORE) of the AM64x SoC is set to 0.75 V. SoC Array Core Voltage (VDDR_CORE) and other array core voltages (VDDA_0P85_SERDES0_C, VDDA_0P85_SERDES0, VDDA_0P85_USB0, VDD_DLL_MMC0, and VDD_MMC0) are configured to 0.85 V and are supplied through a common rail.

The SoC has different IO groups. Each IO group is powered by specific power supplies as given in Table 4-6.

Table 4-6 SoC Power Supply
SI.No Power Supply SoC Supply Rails IO Power Group Power
1 VDDAR_CORE VDDA_0P85_SERDES0 SERDES0 0.85
VDDA_0P85_SERDES0_C 0.85
VDDA_0P85_USB0 USB0 0.85
VDD_MMC0 MMC0 0.85
VDDR_CORE CORE 0.85
2 SoC_DVDD3V3 VDDSHV_MCU MCU 3.3
VDDA_3P3_USB0 USB0 3.3
VDDSHV0 General 3.3
VDDSHV1 PRG0 3.3
VDDSHV2 PRG1 3.3
VDDSHV3 GPMC 3.3
VMON_3P3_MCU 3.3
VMON_3P3_SOC 3.3
3 VDDA_1V8_MCU VDDA_MCU MCU 1.8
4 VDDA_1V8_SERDES VDDA_1P8_SERDES0 SERDES0 1.8
5 VDDA_1V8_USB0 VDDA_1P8_USB0 USB0 1.8
6 VDDA_1V8 VDDS_OSC OSC0 1.8
VDDA_TEMP_0/1 1.8
VDDA_PLL_0/1/2 1.8
7 VDDS_DDR VDDS_DDR DDR0 1.1
VDDS_DDR_C 1.1
8

SOC_DVDD1V8

 VDDSHV4 FLASH 1.8
VDDS_MMC0 MMC0 1.8
VMON_1P8_MCU 1.8
VMON_1P8_SOC 1.8
9 VDDSHV_SD_IO VDDSHV5 MMC1 3.3
10 VDDS_MMC0/ADC0_VREFP VDDS_MMC0 MMC0 0