SPRUJC1 April   2024

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Unlocking JTAG With Jacinto7 Security Enabled Devices
  5. 2Steps to Unlock JTAG for HSM Core With TRACE32
    1. 2.1 Modifying the SCI Client Default Security Board Configuration
      1. 2.1.1 PROCESSOR-SDK-RTOS
      2. 2.1.2 PROCESSOR-SDK-LINUX
    2. 2.2 Building the SCI Client Security Board Configuration
      1. 2.2.1 PROCESSOR-SDK-RTOS
      2. 2.2.2 PROCESSOR-SDK-LINUX
    3. 2.3 Modifying the Secondary Bootloader’s x509 Certificate
      1. 2.3.1 Windows Build Environment
      2. 2.3.2 Ubuntu Build Environment
    4. 2.4 Building the Secondary Bootloader
    5. 2.5 Verifying Secondary Bootloader and TIFS is Executing
    6. 2.6 Creating a Downloadable x509 Certificate With a Debug Extension
    7. 2.7 Execution of TRACE32 Unlock Script
    8. 2.8 Attaching to HSM Core With TRACE32

1 Introduction

The Jacinto7 Security Management Subsystem (SMS) is composed of two Arm® Cortex®-M4F cores. The primary core is referred to as the TI Foundational Security Module (TIFS) and executes TI foundational security functions. Furthermore, the secondary core is referred to as the Hardware Security Module (HSM) and is used for running customer or third party security functionality. This user guide describes the process for unlocking JTAG and accessing the HSM (Arm Cortex - M4F Secure Core 1) with Lauterbach’s TRACE32 on Jacinto7 security enabled devices.

GUID-20240212-SS0I-PGST-HGV7-G86VRWNG9DZQ-low.svg Figure 1-1 Security Management Subsystem Generation 2 Architecture