SPRZ357P August   2011  – June 2020 F28M35E20B , F28M35H22C , F28M35H52C , F28M35H52C-Q1 , F28M35M22C , F28M35M52C

 

  1.   F28M35x Concerto MCUs Silicon Errata Silicon Revisions E, B, A, 0
    1. 1 Introduction
    2. 2 Device and Development Support Tool Nomenclature
    3. 3 Device Markings
    4. 4 Usage Notes and Known Design Exceptions to Functional Specifications
      1. 4.1 Usage Notes
        1. 4.1.1  PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
        2. 4.1.2  FPU32 and VCU Back-to-Back Memory Accesses
        3. 4.1.3  Caution While Using Nested Interrupts
        4. 4.1.4  PBIST: PBIST Memory Test Feature is Deprecated
        5. 4.1.5  HWBIST: Cortex-M3 HWBIST Feature is Deprecated
        6. 4.1.6  HWBIST: C28x HWBIST Feature Support is Restricted to TI-Supplied Software
        7. 4.1.7  Flash Tools: Device Revision Requires a Flash Tools Update
        8. 4.1.8  EPI: New Feature Addition to EPI Module
        9. 4.1.9  EPI: ALE Signal Polarity
        10. 4.1.10 EPI: CS0/CS1 Swap
        11. 4.1.11 Major Device Revision
      2. 4.2 Known Design Exceptions to Functional Specifications
    5. 5 Documentation Support
  2.   Trademarks
  3.   Revision History

4.1.9 EPI: ALE Signal Polarity

Revision(s) Affected: A, B, E

On the revision 0 silicon, the polarity of the ALE (address latch enable) signal was active HIGH and it was not configurable. On new silicon revisions, a configuration bit (ALEHIGH) has been added in existing host bus configuration registers so that the user can configure the polarity of the ALE signal as per system requirement. Reset value of this bit is set to “1” to have the default polarity of ALE as active HIGH so that it is compatible with the revision 0 silicon (‘0’ will make it active LOW). Since this configuration field was reserved in the revision 0 silicon, if the application writes ‘0’ to this field (while configuring other bit fields in this register), there would be no issue for the revision 0 silicon, but the same code will not work on the revision A silicon. This is because ‘0’ means active LOW polarity for ALE on revision A silicon. This bit needs to be set to ‘1’ to make it work on the revision A silicon.