SPRZ579A July   2025  – October 2025 F28E120SB , F28E120SC

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2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
3. 1Usage Notes and Advisories Matrices
   1. 1.1 Usage Notes Matrix
   2. 1.2 Advisories Matrix
4. 2Nomenclature, Package Symbolization, and Revision Identification
   1. 2.1 Device and Development-Support Tool Nomenclature
   2. 2.2 Devices Supported
   3. 2.3 Package Symbolization and Revision Identification
5. 3Silicon Revision 0 Usage Notes and Advisories
   1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts With Repeat Block
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
   2. 3.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7. 3.2.1 Advisory
      8.      Advisory
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      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
6. 4Documentation Support
7. 5Trademarks
8. 6Revision History