2 Terminology

PHY: Refers to the PHY mode of the OSPI and QSPI Drivers

QSPI: Quad Serial Peripheral Interface

OSPI: Octal Serial Peripheral Interface

DDR: Dual Data Rate

SDR: Single Data Rate

DAC: Direct Access Controller

INDAC: Indirect Access Controller

MiBps: Mebibytes per second

PHY:

PHY mode uses a specialized timing circuit to manage memory data transfers. In this mode, each reference clock cycle generates one complete memory clock cycle for standard transfers or half a cycle for double-speed transfers. The system offers four different timing configurations, using either internal signals or external feedback from the memory chip.

When PHY is enabled, the input clock divider is bypassed. As a result, the effective frequency is the input clock frequency. The PHY tuning algorithm calculates the tuning point by varying rxDLL, txDLL, and Read Delay. To learn more about this, see the following FAQ.

TAP:

TAP mode uses an internal reference clock to time data transfers with the memory device. This divides this reference clock by four for standard transfers or by eight for double data rate transfers. This mode only supports a direct (non-loopback) configuration, using the reference clock for data capture timing.

When TAP Mode is enabled, the input clock divider is not bypassed. As a result, the effective frequency is the input clock frequency divided by the input clock divider.

QSPI:

Quad Serial Peripheral Interface - an enhanced SPI variant using four data lines (DQ0-DQ3) for serial data transfer. Supports single/dual/quad modes for different transfer phases, achieving up to 4x bandwidth improvement over standard SPI while maintaining backward compatibility.

OSPI:

Octal Serial Peripheral Interface - an advanced SPI variant using eight data lines (DQ0-DQ7) for serial data transfer. Supports all QSPI modes plus octal mode, enabling even higher bandwidth. Can operate with or without DQS (Data Strobe) signal for source-synchronous data capture.

SDR:

SDR mode transfers data on a single edge of the clock signal, sending one bit per clock cycle per data line. This is the simpler and more traditional clocking scheme that provides good reliability at moderate speeds. In octal SDR mode with eight data lines, the theoretical maximum data rate is eight bits per clock cycle.

DDR:

DDR mode transfers data on both rising and falling edges of the clock signal, effectively doubling the data throughput compared to SDR mode. In octal DDR mode with eight data lines, data is transferred 16 bits per clock cycle (eight bits per edge × two edges).

Protocol (Command-Address-Data):

The protocol mode format is WR-WR-WR, where the first WR represents the command bit width and rate, the second WR represents the command modifier bit width and rate, and the third WR represents the data bit width and rate. The bit width (W) can be one or eight bits. The rate (R) is either S for SDR or D for DDR. SDR transfers the same value on both rising and falling clock edges, while DDR may transfer different values on each edge.

For example, 1S-1S-1S means all phases use 1-bit wide SDR. The notation 8D-8D-8D means all phases use 8-bit wide DDR.

DAC:

Direct access refers to the operation where data interface accesses directly trigger a read or write to Flash memory. It is memory mapped and can be used to both access and directly execute code from external Flash memory.

INDAC:

The aim of the indirect mode of operation is to read significant numbers of bytes from Flash memory without requiring a data interface access to trigger it. Instead indirect operations are controlled and triggered by software via specific control/configuration Indirect Read Transfer registers. The read data is placed into the local SRAM module ready for fast and low latency delivery to any external controller.