STDA054 October   2026 TDA54-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Zonal Architectures
  5. 2Network Processing Accelerator (NPAC)
    1. 2.1 NPAC Architecture
    2. 2.2 NPAC Use Case Examples
    3. 2.3 NPAC Features and Benefits
  6. 3Summary

2 Network Processing Accelerator (NPAC)

Texas Instruments’ (TI) network processing accelerator (NPAC) is a high-performance networking processing engine that offloads networking and security tasks from the main processing cores. The NPAC consists of dedicated hardware accelerators, memory, look-up tables, and programmable RISC-V cores. This combination of deterministic hardware IP blocks and programmable cores enables high-throughput, low-power, low-latency packet processing that can support a wide range of networking applications.

TITDA5x TVN2x AM2G TDA54x NPAC Block DiagramFigure 2-1 TDA54x NPAC Block Diagram

NPAC features or applications:

  • Process millions of packets per second
  • L3 (IP), L4, and VLAN routing and gateway support
  • Security offload (IPSec, SSL, TLS, SecOC, and so forth)
  • Firewall, access control list (ACL), and packet inspection
  • Packetization and depacketization offload
  • Pre-defined, customizable code examples
  • Graph-based programming framework