STDA054 October 2026 TDA54-Q1
| NPAC Feature | Comment |
|---|---|
| Processing offload | Networking functions are offloaded to the NPAC, freeing up SoC cores to perform other tasks. |
| Multi-function | Support multiple functions, including L3 (IP), L4, and VLAN routing, gateway, packetization, depacketization, encryption, decryption, authentication, and firewall filtering. |
| Programmable | Combination of dedicated hardware accelerators and programmable RISC-V cores allows customers to easily configure and customize networking functions. |
| Low power | low latency | Fixed function hardware and high-speed packet bus reduce power and latency. |
| Packet routing | L3 (IP), L4, and VLAN routing offload. |
| Packetization and de-packetization | Packetization and depacketization offload; a direct packet bus connection to system memory reduces latency and increases throughput when SoC processing is required. |
| Firewall and packet filtering | Supports access control list (ACL) filtering and packet inspections, routing traffic to authorized areas only. |
| Encryption, decryption, and authentication | Dedicated, low-latency cryptographic accelerators support CANsec, IPsec, TLS, SecOC, and other cryptographic standards. |
Graphic based programming GUI | An intuitive, easy-to-program graphical model enables customization of NPAC functionality. A library of pre-defined and custom nodes maximizes supported use cases and decreases NPAC programming time. |
| Scalable architecture | Scale networking performance from zonal to central compute gateways on a common hardware architecture maintaining code compatibility. |