SWRS227C March   2020  – December 2024 CC3130

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1.      12
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Current Consumption Summary
    6. 7.6  TX Power Control
    7. 7.7  Brownout and Blackout Conditions
      1. 7.7.1 Brownout and Blackout Voltage Levels
    8. 7.8  Electrical Characteristics for DIO Pins
      1. 7.8.1 Electrical Characteristics: DIO Pins Except 52 and 53
      2. 7.8.2 Electrical Characteristics: DIO Pins 52 and 53
    9. 7.9  Electrical Characteristics for Pin Internal Pullup and Pulldown
    10. 7.10 WLAN Receiver Characteristics
      1.      28
    11. 7.11 WLAN Transmitter Characteristics
      1.      30
    12. 7.12 WLAN Transmitter Out-of-Band Emissions
      1. 7.12.1 WLAN 2.4GHz Filter Requirements
    13. 7.13 BLE/2.4GHz Radio Coexistence and WLAN Coexistence Requirements
    14. 7.14 Thermal Resistance Characteristics for RGK Package
    15. 7.15 Timing and Switching Characteristics
      1. 7.15.1 Power Supply Sequencing
      2. 7.15.2 Device Reset
      3. 7.15.3 Reset Timing
        1. 7.15.3.1 nRESET (32-kHz Crystal)
        2. 7.15.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32kHz Crystal)
        3. 7.15.3.3 nRESET (External 32kHz Crystal)
          1. 7.15.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32kHz Crystal)
      4. 7.15.4 Wakeup from HIBERNATE Mode
        1. 7.15.4.1 nHIB Timing Requirements
      5. 7.15.5 Clock Specifications
        1. 7.15.5.1 Slow Clock Using Internal Oscillator
          1. 7.15.5.1.1 RTC Crystal Requirements
        2. 7.15.5.2 Slow Clock Using an External Clock
          1. 7.15.5.2.1 External RTC Digital Clock Requirements
        3. 7.15.5.3 Fast Clock (Fref) Using an External Crystal
          1. 7.15.5.3.1 WLAN Fast-Clock Crystal Requirements
        4. 7.15.5.4 Fast Clock (Fref) Using an External Oscillator
          1. 7.15.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
      6. 7.15.6 Interfaces
        1. 7.15.6.1 Host SPI Interface Timing
          1. 7.15.6.1.1 Host SPI Interface Timing Parameters
        2. 7.15.6.2 Flash SPI Interface Timing
          1. 7.15.6.2.1 Flash SPI Interface Timing Parameters
        3. 7.15.6.3 DIO Interface Timing
          1. 7.15.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3V)
            1. 7.15.6.3.1.1 DIO Output Transition Times (Vsupply = 3.3V) #GUID-01C4FDBB-69B0-4F3E-AD14-CDACB1CFA3A4/SWAS03298470_
          2. 7.15.6.3.2 DIO Input Transition Time Parameters
            1. 7.15.6.3.2.1 DIO Input Transition Time Parameters
    16. 7.16 External Interfaces
      1. 7.16.1 SPI Flash Interface
      2. 7.16.2 SPI Host Interface
      3. 7.16.3 Host UART Interface
        1. 7.16.3.1 5-Wire UART Topology
        2. 7.16.3.2 4-Wire UART Topology
        3. 7.16.3.3 3-Wire UART Topology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Device Features
      1. 8.2.1 WLAN
      2. 8.2.2 Network Stack
      3. 8.2.3 Security
      4. 8.2.4 Host Interface and Driver
      5. 8.2.5 System
    3. 8.3 Power-Management Subsystem
      1. 8.3.1 VBAT Wide-Voltage Connection
    4. 8.4 Low-Power Operating Modes
      1. 8.4.1 Low-Power Deep Sleep
      2. 8.4.2 Hibernate
      3. 8.4.3 Shutdown
    5. 8.5 Memory
      1. 8.5.1 External Memory Requirements
    6. 8.6 Restoring Factory Default Configuration
    7. 8.7 Hostless Mode
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection
      3. 9.1.3 Typical Application
    2. 9.2 PCB Layout Guidelines
      1. 9.2.1 General PCB Guidelines
      2. 9.2.2 Power Layout and Routing
        1. 9.2.2.1 Design Considerations
      3. 9.2.3 Clock Interface Guidelines
      4. 9.2.4 Digital Input and Output Guidelines
      5. 9.2.5 RF Interface Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Tools and Software
    2. 10.2 Firmware Updates
    3. 10.3 Device Nomenclature
    4. 10.4 Documentation Support
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

8.4.1 Low-Power Deep Sleep

The LOW-POWER DEEP SLEEP (LPDS) mode is an energy-efficient and transparent sleep mode that is entered automatically during periods of inactivity based on internal power optimization algorithms. The device can wake up in less than 3ms from the internal timer or any incoming host command. The typical battery drain in this mode is 115µA. During LPDS mode, the device retains the software state and certain configuration information. The operation is transparent to the external host; thus, no additional handshake is required to enter or exit LPDS mode. Advanced features of long sleep intervals and IoT low power for extending LPDS time for up to 22 seconds while maintaining a Wi-Fi connection are also supported.