SWRS246D November   2020  – May 2025 AWR6843AOP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Pin Functions - Digital and Analog [ALP Package]
    3. 6.3 Pin Attributes
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  Power Save Mode
    9. 7.9  RF Specification
    10. 7.10 CPU Specifications
    11. 7.11 Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    12. 7.12 Timing and Switching Characteristics
      1. 7.12.1  Antenna Radiation Patterns
        1. 7.12.1.1 Antenna Radiation Patterns for Receiver
        2. 7.12.1.2 Antenna Radiation Patterns for Transmitter
      2. 7.12.2  Antenna Positions
      3. 7.12.3  Power Supply Sequencing and Reset Timing
      4. 7.12.4  Input Clocks and Oscillators
        1. 7.12.4.1 Clock Specifications
      5. 7.12.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.5.1 Peripheral Description
        2. 7.12.5.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.5.2.1 SPI Timing Conditions
          2. 7.12.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 7.12.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 7.12.5.3 SPI Peripheral Mode I/O Timings
          1. 7.12.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-F179918D-8747-4E9F-AE33-23F33763D52C/T4362547-70 #GUID-F179918D-8747-4E9F-AE33-23F33763D52C/T4362547-71 #GUID-F179918D-8747-4E9F-AE33-23F33763D52C/T4362547-73
        4. 7.12.5.4 Typical Interface Protocol Diagram (Peripheral Mode)
      6. 7.12.6  LVDS Interface Configuration
        1. 7.12.6.1 LVDS Interface Timings
      7. 7.12.7  General-Purpose Input/Output
        1. 7.12.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.12.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 7.12.9  Serial Communication Interface (SCI)
        1. 7.12.9.1 SCI Timing Requirements
      10. 7.12.10 Inter-Integrated Circuit Interface (I2C)
        1. 7.12.10.1 I2C Timing Requirements
      11. 7.12.11 Quad Serial Peripheral Interface (QSPI)
        1. 7.12.11.1 QSPI Timing Conditions
        2. 7.12.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.12.11.3 QSPI Switching Characteristics
      12. 7.12.12 ETM Trace Interface
        1. 7.12.12.1 ETMTRACE Timing Conditions
        2. 7.12.12.2 ETM TRACE Switching Characteristics
      13. 7.12.13 Data Modification Module (DMM)
        1. 7.12.13.1 DMM Timing Requirements
      14. 7.12.14 JTAG Interface
        1. 7.12.14.1 JTAG Timing Conditions
        2. 7.12.14.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.12.14.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interface
      4. 8.3.4 Host Interface
      5. 8.3.5 Main Subsystem Cortex-R4F
      6. 8.3.6 DSP Subsystem
      7. 8.3.7 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
    5. 8.5 Boot Modes
      1. 8.5.1 Flashing Mode
      2. 8.5.2 Functional Mode
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ALP, 15 × 15 mm

12 Revision History

Changes from July 31, 2022 to May 1, 2025 (from Revision C (July 2022) to Revision D (May 2025))

  • Applications: Applications updatedGo
  • Figure 4-1: Updated block diagram.Go
  • (Device Comparison) AWRL6432 and AWRL1432 devices addedGo
  • (VPP Specification for One-Time Programmable (OTP) eFuses): Section added.Go
  • (Power Save Mode): Section added.Go
  • RF Specification: Phase noise updated to -93dBc/Hz from -92dBc/HzGo
  • RF Specification: Transmitter EIRP number updated to 16dBm from 15dBmGo
  • Figure 7-5 (Device Wake-Up Sequence): Logic diagram updated.Go
  • Updated/Changed Frequency tolerance from "–50 and 50" to "–200 to 200"Go
  • (QSPI Timings):Updated QSPI cycle time from 25 to 12.5Go
  • (Boot Modes): Section added.Go

Changes from June 2, 2021 to July 31, 2022 (from Revision B (June 2021) to Revision C (July 2022))

  • (Features) : Updated Functional-Safety Compliance Certification Collateral; Details on Device Security added; Mentioned the specific operating temperature range for the mmWave SensorGo
  • (Description): Updated/Changed Description to add more details about the device subsystems.Go
  • (Device Comparison) Removed information on Functional-Safety compliance from the table and instead added a table-note for this and LVDS Interface; Additional information on Device security updated.Go
  • (QSPI Timings):Updated/Changed Setup Time from 7.3us to 5us and Hold Time from 1.5us to 1us for QSPI TimingsGo
  • (QSPI Timings): Updated/Changed Delay time, sclk falling edge to d[1] transition i.e. [Q6, Q9] from -3.5us to -2.5us (Min) and 7us to 4us (Max) in QSPI Switching CharacteristicsGo
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go