SWRZ154 August   2023 IWR1843AOP

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#04A
    3.     MSS#05A
    4.     MSS#13
    5.     MSS#17
    6.     MSS#18
    7.     MSS#19
    8.     MSS#20
    9.     MSS#21A
    10.     MSS#22
    11.     MSS#23
    12.     MSS#24
    13.     MSS#25
    14.     MSS#26
    15.     MSS#27
    16.     MSS#28
    17.     MSS#29
    18.     MSS#30
    19.     MSS#31
    20.     MSS#32
    21.     MSS#33
    22.     MSS#34
    23.     MSS#35
    24.     MSS#37B
    25.     MSS#38A
    26.     MSS#39
    27.     MSS#40
    28.     MSS#42
    29.     MSS#43A
    30.     MSS#44
    31.     MSS#45
    32.     ANA#08A
    33.     ANA#09A
    34.     ANA#10
    35.     ANA#11A
    36.     ANA#12A
    37.     ANA#13B
    38.     ANA#15
    39.     ANA#16
    40.     ANA#17A
    41.     ANA#18B
    42.     ANA#20
    43.     ANA#21B
    44.     ANA#22A
    45.     ANA#24A
    46.     ANA#27
    47.     PACKAGE#02A
  7. 6Trademarks
  8. 7Revision History

MSS#20

Radar Frame Stuck due to Missing Synchronizer Logic in Hardware

Revision(s) Affected:

Description:

Radar Sub System Internal Frame Clock is triggered by rlSensorStart API which starts the Radar Frame. Occasionally the rlSensorStart API does not trigger the clock due to missing synchronizer logic in hardware.

Implication: A DMA read from an unimplemented address can result in a DMA hang condition. In the resulting state the DMA will not respond to any further DMA requests.

Workaround(s):

The issue is frequent if FRC clock source is changed. Ensure that FRC Clock source is not changed.