TIDUBQ7B April 2016 – July 2026
The square waveforms are generated using one additional signal, called BASE_PWM, and the inverted version, named BASE_PWM_N, with the help of resistor divider networks, see R30-R38 in TIDA-00848 schematic, with 1MΩ and 2MΩ, respectively. In addition, the R28 and R29 resistor divider again uses this 1/3-to-2/3 ratio, the resistor values are also 1MΩ and 2MΩ. The current flowing through the SEG_BASE_COMMON is, at worst, shared by the 21 segment lines, when all 84 LCD segments are on.
While the operation of the U2 SN74AHC1G04 inverter has been tested successfully, a significant drawback of continuous extra current flowing through the resistor network R28 and R29 was identified. Thus, the final implementation (optimized for lower power consumption) removed the inverter and repurposed the DIO_27 pin of the CC1312 as the BASE_PWM_N signal, which is simply the inverted version of the BASE_PWM. By setting the DIO_27 or BASE_PWM_N to output low state while the LCD is inactive, the current through R28 and R29 is eliminated.
The COM and Segment electrodes in any segmented LCD form at their intersection a capacitor, with the liquid crystal as dielectric matter in between them. In a 4-MUX display, one LCD segment pin is internally connected to 4 (or fewer) segments: pin segment 1 (S1) of the BTL002 connects to the 1A, 1B, 1C, and T1 segments on the display—see the left column for Pin1 in Figure 3-2. Note that and each of these segments connects to a different COM plane (COM line) to enable a time multiplexing control of each segment.
The required voltage to drive a segment LCD device has to be DC free in respect to 0 VLCD, thus after driving the common plane (COM signal) a second phase is needed with the reversed polarity, see Technical Information and Application Notes.
Thus for the BTL002 display, there must be 4 COM × 2 = 8 sub-divisions in every single frame sent to the LCD. This is shown in for the COM0 line with the fframe period; the frame rate is commonly selected between 25 frames per second (fps) for flicker-free LCD viewing and maximum of 60Hz to keep current consumption at a reasonable value.
In the TIDA-00848 source code project, the following definitions have been made:All these functions have been implemented in the LCD resource for the SCE module, which is running at 2MHz for lowest power consumption.