TIDUCL0 January 2017
The three-phase inverter with two MOSFETs in parallel forms the power stage. Figure 3 shows one leg of the power stage, which consists of two power blocks. Each power block consists of two MOSFETs connected as a high-side and low-side FET. This device uses TI's patented stacked die technology in order to minimize parasitic inductances while offering a complete half bridge in a space saving thermally enhanced DualCool 5×6 mm package. With an exposed metal top, this power block device allows for simple heat sink applications to draw out heat through the top of the package and away from the PCB, for superior thermal performance at the higher currents demanded by many motor control applications.
The decoupling capacitors C18 and C19 are placed close across each power blocks to reduce the ringing in the supply lines because of the parasitic inductance added by the sense resistor and the power track.
NOTE
Connect the decoupling capacitors very near to the corresponding MOSFET legs for better decoupling. An improper layout or position of the decoupling capacitors can cause undesired VDS switching voltage spikes.
The DC bus current is measured using the current shunt resistors R13 and R15 mounted on the DC bus return path. The sensed currents are fed to the MCU through the current shunt amplifiers. The sense resistor is mainly used to measure the average battery current. The peak current in MOSFET is measured by monitoring the VDS.