TIDUF06 August   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 PCB and Form Factor
      2. 2.2.2 Power Supply Design
        1. 2.2.2.1 POC Filter
        2. 2.2.2.2 Power Supply Considerations
          1. 2.2.2.2.1 Choosing External Components
          2. 2.2.2.2.2 Choosing the Buck 1 Inductor
          3. 2.2.2.2.3 Choosing the Buck 2 and Buck 3 Inductors
          4. 2.2.2.2.4 Functional Safety
    3. 2.3 Highlighted Products
      1. 2.3.1 DS90UB953-Q1
      2. 2.3.2 TPS650330-Q1
      3. 2.3.3 IMX623
    4. 2.4 System Design Theory
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Required Hardware
      1. 3.1.1 Hardware Setup
      2. 3.1.2 FPD-Link III I2C Initialization
      3. 3.1.3 IMX623 Initialization
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
        1. 3.2.1.1 Power Supplies Startup
        2. 3.2.1.2 Power Supply Startup – 1.8 V Rail and Serializer PDB Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 Power Supplies Start Up
        2. 3.2.2.2 Power Supply Output Voltage Ripple
        3. 3.2.2.3 Power Supply Load Currents
        4. 3.2.2.4 I2C Communications
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 PMIC Layout Recommendations
      2. 4.3.2 PCB Layer Stackup
      3. 4.3.3 Serializer Layout Recommendations
      4. 4.3.4 Imager Layout Recommendations
      5. 4.3.5 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
  11. 6Trademarks

4.3.3 Serializer Layout Recommendations

Trace impedance is one critical aspect to the CSI-2 lane routing. For trace impedance to be within specifications and within range of each other, the length and width of the trace plays a factor in this. To achieve tight impedance specs, length specifications also need to be strict within the positive-to-negative differential pair length and pair-to-pair length. If the length is not matched, at these high-data switching speeds, the data can arrive at the 953 at different times and cause issues of synchronization between data and clock. The length difference between the positive and negative differential pair trace should be within 5 mils of each other. For length matching between each CSI-2 lane pair, the difference must be kept within 25 mils.

GUID-20220426-SS0I-GS6D-6NXH-Q9KS6HBXKVMG-low.pngFigure 4-4 CSI Routing Matching

The last key points to address with CSI-2 routing is crosstalk and reflections. To reduce the effects of crosstalk between lanes, spacing between each differential lane must be at least three times the signal trace width. In addition, keep vias and bends on the traces to a minimum. Bends must be as equal as possible in the number of left and right bends, and the angle of the bend must be greater than or equal to 135 degrees.

Decoupling capacitors need to be located very close to the supply pin on the serializer. Again, this requires that the user consider the path of the supply current and the return current. Keeping the loop area of this connection small reduces the parasitic inductance associated with the connection of the capacitor. Due to space constraints, ideal placement is not always possible. For decoupling capacitors placed on the opposite layer of the serializer, the return path to the serializer thermal pad should be minimized. Smaller value capacitors that provide higher frequency decoupling must be placed closest to the device.

For this application, a single-ended impedance of 50 Ω is required for the coax interconnect. Whenever possible, this connection must also be kept short. Figure 4-5 shows the routing of the high-speed serial line, highlighted by the yellow line. The total length of the yellow line is about ½ inch.

GUID-E9E97B74-8B9F-4D57-9D63-CE5186D282AD-low.pngFigure 4-5 DOUT Path on Base Board