TPS16410 E-Fuse Test Results

To test the features of the TPS16410 e-fuse, an electronic load is used to draw the power from the supply. J17 in Figure 3-4 below shows the connection point for the E-load. The input power used for this test is a DC power supply operating at various voltages to capture the controlled start-up, the overvoltage and undervoltage protection response, in addition to the overcurrent protection and power limiting.

Figure 3-4 Board Connections Used to Test the TPS16410 E-Fuse

EFUSE startup, no load

Figure 3-5 below shows the start-up behavior of the TPS16410 when a voltage is applied to the input of the device and incrementally increased to just above the undervoltage threshold. Once the voltage reaches this point, the output voltage of the TPS16410 is enabled and there is a 1.98ms delay from the time the device is enabled to the time the input voltage is available on the output for downstream device power.

Figure 3-5 E-Fuse Start-up at No Load

Figure 3-6 below shows the response of the TPS16410 when power is turned on with a high load active. In this instance, the TPS16410 starts to regulate the power as expected but due to the inrush current associated with the already active load, the e-fuse eventually goes into a fault condition after approximately 200ms from the time the input voltage is turned on. The input power is limited to 14.30W for this test, yielding an error of approximately 3%.

Figure 3-6 E-Fuse Regulation During Voltage Turn-On at High Load

Power Limiting

The TPS16410 circuit is designed to limit the power consumption to 13.65W for this design. For applications requiring a higher power limit (24VAC input), the equations in Section 2.2 can be used to adjust the power limit, or the device can be bypassed for evaluation.

If the device junction temperature reaches the thermal shutdown threshold (TSD), the internal FET is turned off. When the TPS16410 detects thermal overload, the device remains off until cooled down to T_SDHYS. Once the TPS16410 has cooled down by T_SDHYS, the device remains off for an additional delay of t_TSD,RST after which the device automatically retries to turn on if the device is still enabled. During thermal shutdown, the fault pin FLT pulls low to signal a fault condition.

Figure 3-7 below shows the power regulation of the device approaching the 13.7W threshold. The electronic load is set to constant power and gradually increased towards the power limit. As the load increases, the output voltage begins to droop to keep the power below the limit threshold. As the load is increased even more, the device disables the output. The TPS16410 has a power regulation accuracy of 99.5% for a P_LIM of 13.65W.

Figure 3-7 E-Fuse Power Limiting

Input Overvoltage protection

The TPS16410 device incorporates circuits to protect the system during overvoltage conditions. A voltage more than the V_OVLO threshold on the OVLO pin turns off the internal FET and protects the downstream load. The reference design is designed with overvoltage protection voltage of 28V with an input voltage of 24VDC and approximately 40V for a 24VAC input voltage. Figure 3-8 shows the overvoltage shut down at 28.13V, yielding an OVP accuracy of 99.5% for a 28V OVP threshold.

Figure 3-8 E-Fuse Input Overvoltage Protection Response

LMR38020 15V Power Rail Test Results

To test the efficiency of the LMR38020 across loads of 100mA to 1A, both 24VAC as well as 24VDC is provided to J18 and J19, respectively. An electronic load is used to create the specific load conditions for each test. The input voltage, the output voltage, and the output current ripple measurements are taken at the expected maximum allowable load while staying under the 15W total power limit.

Figure 3-9 below shows the voltage ripple of both input and output voltages in addition to the output current ripple for a 1A load on the LMR38020. At this load, the total consumption is right under the limit set by the E-fuse. The input voltage ripple at 1A load is approximately 592mV _pk-pk, while the output voltage ripple is approximately 186mV _pk-pk. The output current to the load shows a current ripple of approximately 9.3mA, or about 9.3% ripple _pk-pk.

Figure 3-9 LMR38020 Output Voltage Ripple at 1A Load

Efficiency over load test results:

Table 3-1 below shows the test data for a 24VDC input to the LMR38020 with an electronic load on the output to the device. The load current range is increased from 100mA to 1A in 50mA steps.

Figure 3-10 below shows the efficiency over load current. The efficiency across all load values is greater than 90%, peaking at 96% efficiency at a 450mA load current.

Figure 3-10 LMR38020 Efficiency Over Load With 24VDC Input

The same test is done for a 24VAC rectified input to the LMR38020, sweeping the load current again from 100mA to 1A in 50mA step sizes. This data is captured in Table 3-2 below.

Figure 3-11 below shows the efficiency versus load current for a rectified 24VAC input voltage to the LMR38020. The efficiency peaks at 93% and has a relatively flat efficiency curve from 350mA to 900mA load current.

Figure 3-11 LMR38020 Efficiency Over Load With 24VAC Input

TPS62932 3.3V Power Rail Test Results

The test procedure for testing the efficiency of the TPS62932 under varying load conditions is identical to the test for the LMR38020 above. In this case, we are pulling 100mA to 1A from the 3.3VDC power rail while providing 15VDC to the input of the buck. This is done to isolate the performance of the 3.3VDC buck.

For the load on the 3.3V power rail, a worst-case scenario of 750mA is used as the load current to measure the input voltage ripple, output voltage ripple, and the output current ripple. Figure 3-12 below shows the ripple for each of the aforementioned parameters. The input voltage ripple pk-pk is 192mV, or approximately 1.3%. The output voltage ripple pk-pk is about 80.8mV, or about 2.4%. The output current ripple pk-pk is around 5.3mA or approximately 0.7%.

Figure 3-12 TPS62932 Ripple at 750mA Load

Efficiency Results:

Table 3-3 below shows the data captured for the efficiency test of the TPS62932. This test is identical to that of the LMR38020 for load current test values, although the 3.3V power rail total power consumption is much lower since the power rail is only used for the MCU and the board peripherals.

Figure 3-13 below shows the efficiency of the TPS62932 versus load current. The efficiency peaks at 92.61% at an 850mA load, but since the total load on the 3.3V rail is much lower than this, the efficiency during operation has an average efficiency in the mid 80% range.

Figure 3-13 TPS62932 Efficiency Over Load

DRV8316 Test Results

To test the operational functionality of the DRV8316C, an actual end-user product is used to test performance of the TI device. The portions of the product used by this reference design are the Hall effect sensors, the BLDC damper motor, and the gears which effectively transfer the energy of the motor turning to the damper. The main test setup is shown below in Figure 3-14. As the motor rotates, a small portion of the gear network that is available is leveraged along with a magnet placed inside the gear cavity for rotation information. The TMAG5273 board is then mounted directly over the magnet/gear and sends angle data back to the main board during operation.

Figure 3-14 BLDC Damper Control Test Setup

One important note regarding the damper motor/gear is that the rotation to the left requires a higher current, while rotating to the right requires much less current. In this section, over to right (OTR) refers to the lower current rotation of the damper to the right while over to left represents the higher current rotation of the BLDC motor to the left.

A secondary TMAG5273 board is employed as a means of remotely detecting the damper position due to the size of the reference design and lack of mounting options for the board to the product. the TMAG5273 remote board is shown in Figure 3-15 below.

Figure 3-15 TMAG5273 Remote Sensing Board for BLDC Motor Position Sensing

Figure 3-16 below shows the motor voltage output on each of the 3 phases during OTL operation. The output to the BLDC motor is 120⁰ between each phase and the output voltage to the BLDC motor is ranges from 15.38V to 15.73V for each output phase.

Figure 3-16 DRV8316C Voltage Output for Each Phase

DRV8316C phase current during operation: Figure 3-17 Below shows the output current for each phase of the BLDC motor during OTL operation. The phase current waveforms are 120 degrees between phase with a total RMS current of 474.6mA. The RMS current is captured during the high current rotation to the left.

Figure 3-17 DRV8316C Output Current During Motor Operation

The waveform below in Figure 3-18 shows the current at the input to the DRV8316C during OTL operation of the BLDC motor. The current consumed by the DRV8316C peaks at approximately 187mA while driving the sensored BLDC motor apparatus with an RMS value of 190.1mA over the duration of movement. The Input voltage is AC coupled to extract the voltage ripple during operation. The voltage ripple is approximately 201mV during the high load rotation of the damper motor to the left.

Figure 3-18 DRV8316C Input Current and Input Voltage Ripple During Operation

Figure 3-19 below shows the control signals from a single output phase of the MSPM0 (both INH and INL) as well as the current output from the SO pin during OTL operation.

The SOx pin on the DRV8316C outputs an analog voltage proportional to current flowing in the low side FETs multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels which can be set by the GAIN pin (in hardware device variant) or the GAIN bits (in SPI device variant). The current sense is implemented with the sense FET on each low-side FET of the DRV8316C device. This current information is fed to the internal I/V converter, which generates the CSA output voltage on the SOx pin based on the voltage on VREF pin and the Gain setting.

Figure 3-19 DRV8316C INH, INL, and SOx During Motor Operation (OTL)

Figure 3-20 shows the same outputs during the OTR operation. The INH and INL control signal along with the SOx are much shorter in duration with an increased frequency during the faster rotation of the damper motor in this scenario.

Figure 3-20 DRV8316C INH, INL, and SOx During Motor Operation (OTR)

DRV8428 Test Results

The DRV8428 testing is very similar to that of the BLDC damper motor, but instead leveraging a 24VDC bipolar stepper motor. A magnet is affixed to the back of the motor as shown below in Figure 3-21, and this is used for the position control loop in the case of 0V-10V or 4mA-20mA control, and simply as a position verification measure in the case the stepper motor is controlled by a temperature-based control loop.

Figure 3-21 Stepper Motor Setup with Position Magnet

Figure 3-22 shows the load test results of the DRV8428 device driving a bipolar stepper motor in full stepping mode using a single-pin interface. In full-stepping mode, the full-bridge operates in either of two modes (forward or reverse mode) with a phase shift of 90° between the two windings. Figure 3-22 shows the STEP voltage, OUTA winding current, and OUT B winding.

Figure 3-22 DRV8428 Phase Output and STEP Control Signal

DRV8428 Stepper Motor Drive efficiency:

To test the efficiency of the DRV8428, the input DC voltage to the device is swept from 15VDC to 24VDC while observing the current output of the power supply during operation. Current probes and voltage meters are used on each output from the DRV8316C during motor operation as well to acquire the RMS voltage and RMS current for each phase. The test is performed twice leveraging different decay mode settings to highlight the efficiency improvements that can be achieved.

Figure 3-23 below shows the current and voltage outputs for the DRV8428 during operation with the decay pin set to 0 through a GPIO from the MSPM0 (smart tune ripple control enabled). Smart tune Ripple Control operates by setting an I_VALLEY level alongside the I_TRIP level. When the current level reaches I_TRIP, instead of entering slow decay until the t_OFF time expires, the driver enters slow decay until I_VALLEY is reached. Slow decay operates similar to mode 1 in which both low-side MOSFETs are turned on allowing the current to recirculate. In this mode, t_OFF varies depending on the current level and operating conditions. This method allows much tighter regulation of the current level increasing motor efficiency and system performance. Smart tune Ripple Control can be used in systems that can tolerate a variable off-time regulation scheme to achieve small current ripple in the current regulation. The V_REF pin is set to 1.5V from the MSPM0 DAC through firmware. The M0 pin of the DRV8428 is driven to 0, while the M1 pin is connected through a 330kΩ resistor to ground, setting the microstepping mode to full step (2-phase excitation) with 71% current.

The measured RMS voltage and current for AOUT 1 is 1.69V and 367.1mA RMS, and the BOUT 1 is 2.08V and 368.4mA respectively. The off-time for each phase is 9.86ms, and both outputs are 90 degrees phase shifted.

Figure 3-23 DRV8428 Output Current and Voltage with Smart Tune Ripple Control

Table 3-4 below shows the test results for the DRV8428 efficiency during operation with the decay mode set to smart tune ripple control. The input DC Power is gradually increased and the RMS output voltage/current is recorded to calculate the motor drive efficiency.

Figure 3-24 below shows the resulting motor drive efficiency over the input DC power.

Figure 3-24 DRV8428 Efficiency Over Input Power

For the second test, the decay mode is set to HI-Z which leverages the smart tune dynamic decay mode. This decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle to prevent regulation loss. If a long drive time must occur to reach the target trip level, the decay mode becomes less aggressive (remove fast decay percentage) on the next cycle to operate with less ripple and more efficiently. On falling steps, smart tune Dynamic Decay automatically switches to fast decay to reach the next step quickly. The V_REF remains at 1.5V set with the MSPM0 DAC, utilizing full step 2 phase excitation with 71% current. Figure 3-25 below shows the output of both AOUT 1 and BOUT 1during motor operation. AOUT1 has an RMS voltage of 2.36V and an RMS current output of 317.4mA. For BOUT 1 the RMS voltage is 2.73V and RMS current is 320.1mA. The off-time in this mode is approximately 7.66ms.

Figure 3-25 DRV8428 Output Current and Voltage With Smart Tune Dynamic Decay

Table 3-5 below shows the recorded data for each incremental input voltage value along with the calculated efficiency for each.

Figure 3-26 below shows the efficiency and the total phase output current plots across the input power range for the DRV8428 with smart tune dynamic decay enabled. In this test, the efficiency numbers are considerably better and proportional to the input supply voltage, peaking at approximately 97% at 24VDC input voltage.

Figure 3-26 DRV8428 Efficiency over Input Power