TIDUF88 October   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Accuracy of Bus Voltage Measuring
      2. 2.2.2 Shunt Current Measuring
      3. 2.2.3 Insulation Impedance Monitor
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ79731-Q1
      2. 2.3.2 TPSI2140-Q1
      3. 2.3.3 ISO7841
      4. 2.3.4 SN6507
      5. 2.3.5 TPS7B6950
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Bus Voltage Accuracy
      2. 3.3.2 Current Sensing Accuracy
      3. 3.3.3 Insulation Impedance Accuracy
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

3 Hardware, Software, Testing Requirements, and Test Results

The key performances of the TIDA-010272 were tested in a TI lab, and the end equipment used and test processes and results are described in this section.

Table 3-1 describes the connections for the TIDA-010272 board.

Table 3-1 Positive High-Voltage Connector
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J24-1 N/A N/A
J24-2 BATP Positive terminal of battery
J24-3 RACKP Positive terminal of rack
Table 3-2 Negative High-Voltage Battery Connector
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J22-1 RACKN Negative terminal of rack
J22-2 BATN Negative terminal of battery
J22-3 N/A N/A
Table 3-3 Host Interface
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J8-1 ISO_OC2_R Isolated over current alarm from BQ79731 CSADC1
J8-3 ISO_SCLK
J8-5 ISO_GND
J8-7 ISO_MOSI_RX Isolated MOSI/RX of BQ7973x
J8-9 ISO_nCS
J8-2 ISO_nFAULT_OD BQ7973x NFAULT pin
J8-4 ISO_OC1_R Isolated overcurrent alarm from BQ79731 CSADC2
J8-6 USB2ANY_3.3V Isolated USB2ANY 3.3V
J8-8 ISO_MISO_TX Isolated MISO/TX of BQ7973x
J8-10 ISO_nUART_SPI
Table 3-4 Current Sensor 1 Connector
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J28-1 SRP1_RES Current sensing positive terminal for channel 1
J28-2 SRN1_RES Current sensing negative terminal for channel 1
J28-3 GND GND of BQ7973x
J28-4 NTC1_RTN Return pin of thermistor 1
J28-5 NTC1_SNS Sensing pin of thermistor 1
Table 3-5 Current Sensor 2 Connector
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J29-1 SRP2_RES Current sensing positive terminal for channel 2
J29-2 SRN2_RES Current sensing negative terminal for channel 2
J29-3 GND GND of BQ7973x
J29-4 NTC2_RTN Return pin of thermistor 2
J29-5 NTC2_SNS Sensing pin of thermistor 2
Table 3-6 Daisy Chain (COML) Connector
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J35-4 COMLP_ISO COM low-side positive
J35-1 COMLN_ISO COM low-side negative
Table 3-7 Daisy Chain (COMH) Connector
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J37-1 COMHP_ISO COM high-side positive
J37-4 COMHN_ISO COM high-side negative
Table 3-8 Low-Voltage Side Power Supply
CONNECTOR AND
PIN ASSIGNMENTS		 FUNCTION OR
SCHEMATIC NET		 NOTES
J1-1 KL30_IN Positive terminal of 24V DC power supply
J1-2 GND_LV Negative terminal of 24V DC power supply
J1-3 GND_LV Negative terminal of 24V DC power supply