TIDUFG6A December   2025  – June 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System and Interface Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TMS320F28P65x (F28P65x)
      2. 2.3.2 DRV8376
      3. 2.3.3 DP83826A
  9. 3System Design Theory
    1. 3.1 F28P65 Motor Control and Communication Interface
    2. 3.2 Multi-Axis Motor Control Scheme
    3. 3.3 DC Link Decoupling
    4. 3.4 Three-Phase Inverter With DRV8376
    5. 3.5 System Power Management
    6. 3.6 Ethernet Physical Layer
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 TIDA-010992 PCB Overview
      2. 4.1.2 TIDA-010992 Hardware Settings
    2. 4.2 Software Requirements
    3. 4.3 Testing and Results
      1. 4.3.1 Power Management and System Power Up and Power Down
      2. 4.3.2 Current Feedback
      3. 4.3.3 Three-Phase Half-Bridge Motor Driver Power Stage Switch Node
      4. 4.3.4 Multi-Axis Motor Control Scheme Verification
      5. 4.3.5 System Thermal Measurements
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 Layer plots
      4. 5.1.4 Altium Project
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5.     Trademarks
  12. 6About the Author
  13. 7Revision History

3.1 F28P65 Motor Control and Communication Interface

This design leverages F28P65 dual core with lockstep plus CLA and EtherCAT with NMR (9 × 9 mm) package as the motor control and communication controller. The motor control interface includes:

  • Enhanced Pulse Width Modulator (ePWM) – The PWM peripheral is built up from smaller single channel submodules with separate resources that can operate together as required to form a system. This design employs ePWM 1 to 18 for the 6 axis’s three phase motor driver. Each ePWM submodule has two channels A and B to generate two complementary PWM signals with configurable dead-band. For three-phase motor control, total 6 × PWMs are implemented per axis. All these PWM submodules share the same time base clock of 200MHz with up and down count mode and synchronize with each other. Each ePWM module has a synchronization input and an output which can be configured to link to serval sources and events such as EtherCAT sync0 pulse and FSI RXTRIG to close the loop between communication and PWM. In this reference design, EPWM1 of axis 1 is triggered by EtherCAT sync0 pulse and all the other EPWMx modules’ sync IN are triggered by EPWM1’s Sync OUT.
  • Analog-to-digital converter (ADC) – The ADC peripheral is a successive approximation (SAR) style ADC with selectable resolution of 12 bits or 16 bits. Each ADC module consists of a single sample-and-hold (S/H) circuit allowing simultaneous sampling for 3-phase current of a motor. The ADC reference voltage is provided by an external high-precision voltage reference chip REF6230. The corresponding ADC channels start sampling time for each axis are triggered by its own ADC-start-of-conversion (SOCA) and this SOCA event is triggered by the compare event C of each axis EPWM module respectively. The interrupt which is used for the FOC calculation is generated automatically once data conversion is done by ADC SOC.
  • EtherCAT SubordinateDevice Controller (ESC) – The ESC on this F28P65 MCU provides up to 2 Media Independent Interface (MII) ports to connect to EtherCAT PHYs. The process data interface is through 16-bit asynchronous interface. The ESC also provides a 64-bit distributed clocking which can be used internally or externally. Including utilizing SYNC0/1 and LATCH0/1 output signal to synchronize GPIOs, allow inputs from any GPIOs as well as other muxing options for internal device events and supporting timestamping. The ESC has 8 field bus memory management units (FMMUs) which can support all native types of RD/, WR/, RDWR, and built-in features of bit- and byte-addressing. An I2C EEPROM interface is provided to store the information like MAC address. ESC access allocation is to the CPU1 subsystem during initialization.
  • Dual core motor control design – This reference design leverages dual C28x DSP core to perform 6 axis motor control and industrial communication with CPU1 is handling axis 1 and axis 2 control plus EtherCAT application and CPU2 is handling axis 3 to 6 motor control. The memories and peripherals need to be assigned allocation for both CPUs as follows:
  • Flash bank 0 to bank 3 (0x80000 - 0xFFFFF) owned by CPU1 and bank 4 (0x100000 – 0x11FFFF) owned by CPU2
  • DRAM1-4 from 0x00C000 to 0x020000 for data purpose, GSRAM0-2 from 0x008000 to 0x022000 for code purpose are assigned to CPU1. DRAM5 from 0x020000 with 8KB length, GSRAM3-4 from 0x016000 with 16KB length are assigned to CPU2.
  • EPWM1-6 are controlled by CPU1 and EPWM7-18 are controlled by CPU2
  • ADCA and C are controlled by CPU1, ADCB is controlled by CPU2
  • SPIA and D are controlled by CPU1 for axis 1-2 encoder interface and DRV configuration, SPIB and C are controlled by CPU2 for axis 3-6 encoder interface
  • EtherCAT controlled by CPU1
  • CLB1 is controlled by CPU1 for triggering SPIA data transmission, CLB2 and CLB5 are controlled by CPU2 for triggering SPIB and C data transmission.

Figure 3-1 shows the motor control and communication interface of TIDA-010992, and Figure 3-2 shows the axis 1 motor control peripherals example.

TIDA-010992 F28P65 Motor Control and Communication Interface of TIDA-010992 Figure 3-1 F28P65 Motor Control and Communication Interface of TIDA-010992
TIDA-010992 AXIS 1 Motor Control Peripherals Example of TIDA-010992 Figure 3-2 AXIS 1 Motor Control Peripherals Example of TIDA-010992