TIDUFH5 March   2026 TPSI31P1-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1  Control Logic
      2. 2.2.2  Switching Power
        1. 2.2.2.1 Calculation: D
        2. 2.2.2.2 Calculation: 1 – D
        3. 2.2.2.3 Calculation: D + (1 – D)
      3. 2.2.3  Propagation Delay
      4. 2.2.4  MOSFET Selection
      5. 2.2.5  Flyback or Freewheeling Diode Selection
      6. 2.2.6  Sense Resistance Selection
      7. 2.2.7  Input Capacitance Selection
      8. 2.2.8  Output Capacitance Selection
      9. 2.2.9  Design Example #1: Single RSENSE Configuration
      10. 2.2.10 Design Example #2: Double RSENSE Configuration
    3. 2.3 Highlighted Products
      1. 2.3.1 TPSI31P1-Q1
      2. 2.3.2 TPS7A49
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
        1. 4.1.3.1 Use Large Return Planes to Contain Electromagnetic Fields
        2. 4.1.3.2 Minimize High diL/dt Loop Length to Control Oscillations and EMI
        3. 4.1.3.3 Minimize SW Node Area to Improve Ringing and Noise
        4. 4.1.3.4 Minimize Inductor Pad to Limit Parasitic Capacitive Coupling
        5. 4.1.3.5 HV Creepage and Clearance
        6. 4.1.3.6 Layout Prints
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors

4.1.3.2 Minimize High diL/dt Loop Length to Control Oscillations and EMI

Optimize the high di/dt loop by placing the input capacitance close to the switching circuit. Figure 4-2 illustrates the main reference design current loops using a simplified schematic and the reference design layout.

TIDA-050082 TIDA-050082
Figure 4-2 High di/dt Loop Schematic and Layout

In this circuit, S1 represents the MOSFET and S2 represents the flyback diode. Current alternates between the S1 and S2 paths; the current remains continuous where these loops overlap but is discontinuous in the non-overlapping section. This results in a high di/dt loop as the current suddenly transitions from zero to the full load current. Parasitic inductances and capacitances within this loop form resonant circuits that generate voltage oscillations during transitions, as shown in Figure 4-3. Excessive oscillations can exceed absolute maximum specifications, potentially damaging the MOSFET or flyback diode.


TIDA-050082 Ideal vs Realistic VSW Behavior

Figure 4-3 Ideal vs Realistic VSW Behavior

Reducing the high di/dt loop length minimizes the energy stored and released by parasitic elements (WL = 0.5 × LI2) and reduces voltage overshoot (VL = L × diL/dt). Additionally, current in this loop forms a time-varying H-field which can inject current into nearby circuits through mutual inductance, causing more EMI. Minimize the high di/dt loop length and place the input capacitance as close as possible to the MOSFET drain and flyback diode anode for best performance.

If excessive VSW oscillations persist, consider increasing damping by implementing:

  • Increased MOSFET gate resistance to slow turn-on
  • Series resistance at the sense resistor
  • An RC snubber circuit across the SW node to HV−